Input buffer circuit for low power application

Details Input buffer circuit for low power application Input buffer circuit for low power application

2001-02-05

2002-04-02

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Tri-state

With field-effect transistor

C326S057000, C326S056000, C326S086000, C327S108000, C365S230080

Reexamination Certificate

active

06366123

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates in general to complementary MOS (CMOS) circuits to provide low power buffer capability, and more particularly to a CMOS Schmitt trigger with a tri-state feature and a latching circuit.
2. Description of Related Art
Buffer circuits are an integral element in many memory-oriented applications; however, previous applications of the buffer circuits have often resulted in higher power use than necessary. In addition, the previous applications have been subject to multiple transitions of state, when only one transition is desired.
U.S. Pat. No. 3,984,703 (Jorgensen) describes a classic CMOS Schmitt trigger circuit of the prior art. Jorgensen describes an improvement that addresses both high power drain and uneconomical use of die space.
U.S. Pat. No. 5,450,019 (McClure, et al.) describes the use of Schmitt triggers to control a precharge circuit to terminate when the output terminal has reached an intermediate voltage, so that oscillations are minimized as a result of the hysteresis characteristic. Connection of the output terminal to a gate of a precharging driver transistor helps to eliminate overshoot during precharge.
U.S. Pat. No. 6,005,412 (Ranjan, et al.) describes an I/O interface that includes latches, clocks, and conditioning circuits implemented in a custom physical layout to produce a reliable and flexible interface to high frequency busses running a plurality of protocols and signal specifications.
One of the problems with the prior art is the high power dissipation used in the memory applications. Another problem is the possibility of multiple transitions when a Schmitt trigger changes state, due to disturbances in the circuitry.
SUMMARY OF THE INVENTION
An object of the invention is to significantly decrease power dissipation while the circuit is in standby mode.
A further object is to significantly decrease the sensitivity of the circuitry to external disturbances.
A further object is to utilize a tri-state input buffer and feedback latch to accomplish the first objective.
A further object is to utilize the hysteresis effect found in Schmitt Triggers to accomplish the second objective.
The objects are achieved by use of an input buffer receiver with a feedback latch. The latch is activated on a particular transition to insure that a single transition at the input does not result in multiple transitions at the output due to circuit disturbances. This feature is accomplished with a Schmitt trigger and a feedback latch controlled by an enabling signal. Lower power dissipation for an input buffer receiver is another feature of this invention.
In the invention, a traditional input buffer is replaced by a Schmitt trigger type tri-state buffer. The output of the traditional input buffer is subject to noisy input wave shapes. The output of the Schmitt Trigger feeds a feedback latch, which in turn drives the corresponding memory address line A. Because of the combination of the Schmitt trigger and the feedback latch, the output A will be less responsive to circuit disturbances on XA while the chip is selected (CSB is at “0”). This desirable effect is due to the hysteresis in the voltage transfer characteristics of a Schmitt trigger when changing state in either direction.
In addition, A will maintain its current value when CSB is “1,” effectively deselecting the chip, i.e. changes on XA, will not be passed on to the output A while the chip is deselected. Thus, the circuitry driven by A, is in a standby mode while XA may be changing in value due to various causes. This constancy of A results in less power dissipation in the associated driven circuitry.


REFERENCES:
patent: 3984703 (1976-10-01), Jorgensen
patent: 5450019 (1995-09-01), McClure et al.
patent: 5633833 (1997-05-01), Yoon
patent: 5680065 (1997-10-01), Park
patent: 5767696 (1998-06-01), Choi
patent: 6005412 (1999-12-01), Ranjan et al.

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