Input buffer circuit

Details Input buffer circuit Input buffer circuit

1996-08-26

2000-10-31

Santamauro, Jon

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Input noise margin enhancement

326 34, 326 83, 327206, H03K 190185

Patent

active

061408352

ABSTRACT:
The present invention is directed to an input buffer circuit comprising a first inverter for receiving an input signal, a second inverter for receiving an output signal from the first inverter, and a transition time detecting circuit for detecting a transition time of an output signal of a sense amplifier which amplifies and reads a logic value stored in a memory cell. The transition time detecting circuit generates a control signal for a delay depending on a detected level of the transition time. A logic threshold control circuit is provided for feeding the control signal from the transition time detecting means back to an input terminal of said second inverter to control a hysteresis interval of a logic threshold level of an output signal produced in response to the input signal. An output signal from the second inverter is delayed by a delay circuit which provides the delayed output signal to the logic threshold control circuit.

REFERENCES:
patent: 3904888 (1975-09-01), Griffin et al.
patent: 4570091 (1986-02-01), Yasuda et al.
patent: 5336942 (1994-08-01), Khayat
patent: 5341033 (1994-08-01), Koker
patent: 5654645 (1997-08-01), Lotfi
Patent Abstracts of Japan, vol. 016, No. 415, Sep. 2, 1992 (JP-A-04 139870).
Patent Abstracts of Japan, vol. 016, No. 336, Jul. 21, 1992 (JP-A-04 100411).

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