Input buffer capable of reducing delay skew

Details Input buffer capable of reducing delay skew Input buffer capable of reducing delay skew

2011-03-01

2011-03-01

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Pulse shaping

C327S108000, C327S170000

Reexamination Certificate

active

07898287

ABSTRACT:
An input buffer includes a delay compensation unit for combining (a) a first signal obtained by buffering an input signal using another signal, which is out of phase with the input signal, with (b) a second signal obtained by buffering the input signal using a reference voltage signal, to output a third signal.

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