Input buffer

Electronic digital logic circuitry – Interface – Current driving

Reexamination Certificate

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C326S087000

Reexamination Certificate

active

07667492

ABSTRACT:
Methods and corresponding systems for buffering an input signal include outputting a first logic value in response to the input signal being below a lower threshold. A second logic value is output in response to the input signal rising above the lower threshold. Thereafter, the second logic value is maintained until the input exceeds a higher threshold and thereafter falls below the higher threshold. In response to the input signal falling below the higher threshold, the first logic value is output, and maintained at the first logic value, until the input falls below the lower threshold and thereafter rises above the lower threshold.

REFERENCES:
patent: 6084456 (2000-07-01), Seol
patent: 6870402 (2005-03-01), Sylvester et al.
patent: 7005910 (2006-02-01), Becker et al.
patent: 7190206 (2007-03-01), Lee et al.
patent: 7256617 (2007-08-01), Ananthanarayanan et al.
patent: 7276935 (2007-10-01), Camarota

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