Input buffer

Details Input buffer Input buffer

1998-08-11

2001-02-20

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S086000

Reexamination Certificate

active

06191617

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an input buffer, and in particular, to an input buffer that converts an input signal of TTL voltage level to a CMOS voltage level.
2. Background of the Related Art
Generally, a TTL interface is used for interchanging among high-speed communication or current systems rather than a CMOS interface. However, as a CMOS process has been recently applied to a semiconductor integrated circuit, a TTL-to-CMOS interface is widely used.
Accordingly, a CMOS integrated circuit requires an input buffer for converting an input signal of a TTL voltage level to a CMOS voltage level. In particular, to process addresses, data, control signals, etc., a semiconductor memory circuit needs a large number of input buffers for converting a TTL logic signal to a CMOS logic signal and a high processing speed.
FIG. 1
illustrates a first example of a related art input buffer. As shown in
FIG. 1
, the related art input buffer includes an inverter unit
10
and an inverter
103
. The inverter
10
includes a pull-up PMOS transistor
101
and a pull-down NMOS transistor
102
commonly connected between a power supply voltage Vcc and a ground voltage Vss that converts and outputs an externally applied TTL input signal Din. The inverter
103
converts the signal outputted from the inverter unit
10
to an output signal Dout of the input buffer.
The operation of the first related art input buffer will now be described with reference to FIG.
1
. When the external TTL input signal Din of a high level is applied to the inverter unit
10
, the pull-up PMOS transistor
101
of the inverter unit
10
is turned off and the pull-down NMOS transistor
102
is turned on. Thus, the output signal Dout of the first related art input buffer becomes a high level.
When a TTL input signal Din of a low level is externally applied to the inverter unit
10
, the pull-up PMOS transistor
101
of the inverter unit
10
is turned on and the pull-down NMOS transistor
102
is turned off. Thus, the output of the inverter unit
10
becomes a high level and the output signal Dout of the input buffer becomes a low level.
At this time, when the input signal Din of a high level is applied to the inverter unit
10
, both of the pull-down NMOS transistor
102
and the pull-up PMOS transistor
101
are turned on, which generates a static current that flows from the power supply voltage Vcc to the ground voltage Vss. Therefore, static power consumption is unavoidable. In this case, the output voltage level of the inverter
10
does not fully become a low level. For example, the output voltage level is maintained at approximately 1V.
To prevent such problems, a size of the PMOS transistor
101
or the NMOS transistor
102
is modified. However, if only the size is modified, it is difficult or impossible to safely drive an internal circuit having a large load capacitance. Therefore, the inverter
103
should be added to the output terminal. Further, more than a single inverter may be added according to the size of the load. However, each additional inverter can create an undesirable gate delay with respect to the input signal Din.
In the first related art input buffer, the static current and the static power mean the current and power in an interval of the TTL input signal Din will not be transited, but maintained at a high or low level.
FIG. 2
illustrates a second example of a related art input buffer. The second related art input buffer example includes the inverter unit
10
of the related art shown in
FIG. 1
, an inverter
201
for inverting an output signal DOUT, a first switch NMOS transistor
202
for switching. The first switch NMOS transistor
202
has a gate for receiving an output from the inverter
201
and a source for receiving a TTL input signal Din. A cascade second NMOS transistor
203
has a source connected to the drain of the first NMOS transistor
202
and a gate for receiving a first control signal REF
1
. A first PMOS transistor
204
has a drain connected to the drain of the second NMOS transistor
203
, a source for receiving a power supply voltage Vcc, and a gate for receiving a second control signal REF
2
. The first PMOS transistor
204
operates as a current source. A second PMOS transistor
205
for pull-up reinforcement has a gate for receiving an output from the commonly connected drains of the second NMOS transistor
203
and first PMOS transistor
204
. A drain of the second PMOS transistor
205
is connected to an output from the inverter unit
10
and a source is connected to the power supply voltage Vcc.
The operation of the second related art input buffer will be described with reference to FIG.
2
. If the size of the pull-down NMOS transistor
102
is greater than the pull-up PMOS transistor
101
to eliminate the consumption of the static current, which is generated when the TTL input signal Din is a high level in the inverter unit
10
, the pull-up operation performed by the pull-up PMOS transistor
101
becomes weakened and incapable of driving a large load. For example, the size of the pull-up PMOS transistor
101
can be half than that of the pull-down NMOS transistor
102
. To solve the above problem, the second related art input buffer includes not the inverter
103
that leads the gate delay as described in the first related art input buffer, but the PMOS transistor
205
for pull-up reinforcement and the cascade NMOS transistor
203
for controlling the PMOS transistor
205
.
That is, the second PMOS transistor
205
is operated by an output of the first NMOS transistor
202
operated in accordance with the output signal Dout of the input buffer, and the cascade second NMOS transistor
203
, and the current source first PMOS transistor
204
. The second NMOS transistor
203
and the first PMOS transistor
204
are respectively operated in accordance with the externally inputted control signals REF
1
and REF
2
. Further, the output of the second PMOS transistor
205
reinforces the pull-up when the output signal Dout of the input buffer is converted from a low level to a high level. The above description is provided in U.S. Pat. No. 5,406,139.
FIG. 3
illustrates a third example of a related art input buffer. The third related art input buffer includes the inverter unit
10
, a first PMOS transistor
301
having a gate for receiving the externally supplied TTL input signal Din and a source for receiving a ground voltage Vss and an NMOS transistor
302
having a source connected to a drain of the first PMOS transistor
301
and a gate for receiving a power supply voltage Vcc. A second PMOS transistor
303
has a drain connected to a drain of the NMOS transistor
302
and a gate of the pull-up PMOS transistor
101
. The second PMOS transistor
303
also has a gate for receiving the output signal Dout of the inverter unit
10
, and a source for receiving the power supply voltage Vcc.
With reference to
FIG. 3
, the operation of the third related art input buffer will now be described. If the externally applied TTL input signal Din is a high level, the pull-down NMOS transistor
102
of the inverter unit
10
is turned on to pull down the output signal DOUT to a low level. Thus, the second PMOS transistor
303
is turned on. Next, the PMOS transistor
101
of the inverter unit
10
is completely turned off by a high level signal outputted from the second PMOS transistor
303
. Accordingly, the consumption of the static current can be reduced.
On the other hand, if the input signal Din is a low level, the first PMOS transistor
301
is turned on. Thus, the pull-up PMOS transistor
101
of the inverter unit
10
is turned on to transit the output signal Dout to a high level. The above description is reported in IEEE Journal of Solid State Circuits Vol. 30, No. 5,1995, pages 616-620.
However, in the input buffers according to the first and second examples of the related art, if the pull-up PMOS transistor
101
is not completely turned off and the pull-down NMOS transistor
102
is simultaneously turned on, a bias

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