Input and output buffer circuit

Details Input and output buffer circuit Input and output buffer circuit

1996-02-28

1999-03-09

Santamauro, Jon

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 58, 326 86, H03K 190185

Patent

active

058806024

ABSTRACT:
An input and output buffer circuit which is contained in a first circuit operated on a first power source of a first voltage level Vcc1 and is permitted to connect to a second circuit operated on a second power source of a second voltage level Vcc2 higher than the first voltage level Vcc1 including: a driver PMOS transistor with a CMOS gate; a PAD terminal serving as an input and output terminal; and means for controlling the potential of the N well of the driver PMOS transistor in such a manner that when the potential at the PAD terminal is less than Vcc1-Vth, wherein Vth is a threshold voltage of a MOS transistor contained between the driver PMOS transistor and the PAD terminal, the potential of the N well is set at the first voltage level Vcc1; when the potential at the PAD terminal is more than Vcc1+Vth, the potential of the N well is equated with the potential at the PAD terminal; and when the input and output buffer circuit is in the output mode the potential of the N well is switched to the first voltage level Vcc1, whereby the noise resistance and the latch-up resistance of the input and output buffer circuit are improved while preventing a path current flowing through the driver PMOS transistor.

REFERENCES:
patent: 5160855 (1992-11-01), Dobberpuhl
patent: 5406140 (1995-04-01), Wert t al.
patent: 5450025 (1995-09-01), Shay
patent: 5467031 (1995-11-01), Nguyen et al.
patent: 5543733 (1996-08-01), Mattos et al.
patent: 5646550 (1997-07-01), Campbell, Jr. et al.
patent: 5661414 (1997-08-01), Shigehara et al.
T. Nishihara et al., "IBM Moves to Sell LSIs to Outside Customers, . . . " Nikkei Micro-Devices, Oct., 1992, pp. 83-88.

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