Innovated technique to reduce memory interface write mode...

Details Innovated technique to reduce memory interface write mode... Innovated technique to reduce memory interface write mode...

2007-12-13

2009-02-17

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S041000

Reexamination Certificate

active

07492185

ABSTRACT:
The amount of simultaneous switching noise generated through the operation of a programmable device can be reduced by reducing the number of pins switching at the same time. An I/O bank can include a number of I/O pin subsets, or DQS groups, each programmed to switch at a different time so that the switching times of the various pins can be staggered for each system clock cycle. Programmable delay elements can be used to control the delay of each subset. The programmable elements can be placed between the system clock and the output registers in order to delay the receiving of the clock signal by the registers and therefore delaying the switching of the output buffers. The programmable delay elements also can be placed between the output registers and the output buffers in order to delay the receiving of the output data by, and subsequent switching of, the output buffers.

REFERENCES:
patent: 6034541 (2000-03-01), Kopec et al.
patent: 6661254 (2003-12-01), Agrawal et al.
patent: 6971040 (2005-11-01), Volk
patent: 2004/0003194 (2004-01-01), Bodas et al.
patent: 2006/0256877 (2006-11-01), Szczepanek et al.
patent: 2008/0065820 (2008-03-01), Gillingham et al.

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