Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
1999-11-23
2001-02-27
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S620000, C438S014000, C438S017000, C438S018000
Reexamination Certificate
active
06194739
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to in-process electrical testing of integrated circuit (IC) components and, in particular, to GSG RF testers.
2. Description of the Related Art
Semiconductor integrated circuits (ICs) are typically formed in a manufacturing or fabrication process on semiconductor substrates. Silicon wafers are typically employed to provide a common substrate for the components of the ICs. Several ICs (also called dies or chips) are usually formed in each wafer, which is a very thin, flat disc typically about 5-12″ in diameter at the present time. During the manufacturing process, impurities are diffused into each silicon wafer to create transistors and other electronic components of the respective ICs of the wafer. The fabricated components are then interconnected through deposited metal layers to form logic or other functions. Once the wafer is completely processed, it is cut up (diced) into the individual die (chips), which are typically about 5 mm by 5 mm in size. Each die is mounted in a package and the terminals of the chip are connected to the package terminals through a wire bonding operation.
The ICs formed on semiconductor substrates, such as silicon wafers, typically comprise a variety of basic electrical components, such as amplifiers, resistors and the like. The various dies or ICs formed on the wafer are typically arranged in a grid pattern and are thus separated by vertical and horizontal “streets.” It is desirable to verify that such integrated basic components are fabricated according to a design specification and have certain properties or values, e.g., a specified gain, resistance, etc. An individual component cannot readily be tested, however, once integrated into a circuit.
In lieu of testing the integrated components (i.e. the components that are part of the ICs on the wafer), “stand-alone” copies of such basic components are tested. The stand-alone copies are fabricated in some location of the surface of the wafer not occupied by the dies or ICs formed on the wafer, e.g. in the horizontal or vertical streets separating the ICs formed on the wafer. Such stand-alone copies or “target components” have properties or values of gain, resistance, and the like that are representative of such properties of their IC counterparts since they are fabricated using the same process. As such, it may be assumed that the parameters measured for the target components are similar to those of the non-tested integrated components, and it is therefore appropriate to apply the test results for the target components to the integrated components. Such a quality control methodology is referred to as “in-process electrical testing.”
During in-process electrical testing, a signal source and measurement device, usually external, are electrically connected to the stand-alone target component to be tested, or DUT (device under test). Electrical connection is typically effected via microprobes, one of which is attached to an end of a coaxial cable carrying a signal from the signal source, and the other of which is attached to an end of a coaxial cable leading to the measurement device.
On the wafer, the target component is electrically connected to pads. The microprobes contact the pads, thereby electrically connecting the signal source and the measurement device to the target component. The measurement device is typically used to measure various response or performance parameters of the target component, i.e. parameters which characterize the response or performance of the target component.
The pads and the target component, collectively, form a “process monitor” or “device monitor,” sometimes referred to as a “tester”. Some of the wafer surface is typically reserved for such testers. This reserved surface cannot be utilized for devices forming part of the ICs, and, as such, reduces the amount of wafer surface available for the ICs. It is therefore desirable to reduce the amount of wafer surface sacrificed in conjunction with the use of such testers, and to improve the accuracy of such measurements for a given size tester.
SUMMARY
According to the present invention, a wafer configured for in-process testing of electrical components has a plurality of dies disposed on the wafer, wherein adjacent dies are separated from one another by streets. An in-line device monitor having a first port, a second port, and a device-under-test substantially in line with one another is placed within a street, where the device-under-test is between the first and second ports and is electrically coupled to the first and second ports. With such an arrangement, streets having a width of 100 microns and less are suitable for accomodating a RF-device monitor having ground-signal or ground-signal-ground configurations. As a result, accurate GS or GSG RF-device monitors can be provided in narrow streets of wafers, thereby increasing the amount of wafer area available for circuitry.
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U.S. application No. 09/243,377, Carroll, filed Feb. 1, 1999.
Carroll Michael Scott
Ivanov Tony G.
Duane Morris & Heckscher LLP
Lucent Technologies - Inc.
Malsawma Lex H.
Smith Matthew
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