Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1994-04-15
1999-04-20
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
395830, 711150, G06F 1328
Patent
active
058965513
ABSTRACT:
A synchronous dynamic random access memory (SDRAM) device having a master control circuit for accepting a first command and a second command and having an initialization and reprogramming circuit. The master control circuit generates and initialization signal in response to the first command and generates a reprogramming signal in response to the second command. The initialization and reprogramming circuit responds to the initialization signal to control initial programming of a burst control operation feature and responds to the reprogramming signal to control a reprogramming of the burst control operation feature.
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Fast DRAMs Can Be Swapped for SRAM Caches--Electronic Design, Jul. 22, 1993 pp. 55-67.
Synchronous DRAMs Clock at 100 MHz--Electronic Design, Feb. 18, 1993 pp. 45-49.
Micron Technology, Inc., 1993 DRAM data book.
Schaefer Scott
Williams Brett
Micro)n Technology, Inc.
Peikari J.
Swann Tod R.
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