Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2004-09-30
2009-08-18
Lamarre, Guy J (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
07577895
ABSTRACT:
Embodiments include determining seed codes for various numbers of padding bits to be used to pad least significant bit (LSB) positions of a variable length message. Thus, a transmitter having a uniform length cyclic redundancy code (CRC) calculator may accept variable length messages and pad them with various numbers of padding bits to make padded messages having lengths equal to that of the calculator. Then the calculator may calculate the CRC for the padded message using an appropriate seed code as an initial code, so that the CRC for the padded message is equal to a CRC calculated for the variable length message using a calculator having a length equal to the length of the variable length message. Since the CRC calculated by the uniform length calculator is the correct CRC for the variable length message, it may be used by a receiver to verify that a message received is variable length message.
REFERENCES:
patent: 6597526 (2003-07-01), Gray
patent: 6609225 (2003-08-01), Ng
patent: 2003/0159101 (2003-08-01), Hyland et al.
Sadowy Nicholas P.
Venkataramana Krishnamurthy B.
Grossman Tucker Perreault & Pfleger PLLC
Intel Corporation
Lamarre Guy J
Rizk Sam
LandOfFree
Initialization seed to allow data padding for cyclic... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Initialization seed to allow data padding for cyclic..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Initialization seed to allow data padding for cyclic... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4102714