Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1998-10-30
2000-03-21
Hoang, Huan
Static information storage and retrieval
Read/write circuit
Bad bit
3652257, 36523006, G11C 700
Patent
active
060410000
ABSTRACT:
A circuit and method are provided for generating an initializing signal to a master enable fuse circuit on a redundant line decoder. An initialization pulse may be applied to a master enable circuit having a master enable fuse. The master enable fuse may be coupled to a switched voltage supply powered selectively by battery voltage and external Vcc. A circuit for generating the INITIAL signal determines the transition from a power down state to a powered state. A series of delay elements in a generating circuit generates a predetermined initialization pulse of around 3 ns to 5 ns. Half-latch circuits may be initialized between a first and second voltage threshold. Accordingly, the master enable circuits may be set to the proper initialization states for proper operation and minimum power consumption.
REFERENCES:
patent: 5568061 (1996-10-01), McClure
patent: 5825698 (1998-10-01), Kim et al.
patent: 5907514 (1999-05-01), Lee et al.
McClure David C.
Youssef Tom
Galanthay Theodore E.
Hoang Huan
Jorgenson Lisa K.
STMicroelectronics Inc.
Szuwalski Andre
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