Initialisation of a pipelined processor

Details Initialisation of a pipelined processor Initialisation of a pipelined processor

2008-02-28

2011-11-08

Stoynov, Stefan (Department: 2116)

Electrical computers and digital processing systems: support

Digital data processing system initialization or configuration

C713S002000, C708S233000, C712S002000, C712S032000

Reexamination Certificate

active

08055888

ABSTRACT:
A data processing apparatus is disclosed that comprises a pipelined processor, said pipelined processor comprising a processing pipeline for processing instructions in a plurality of stages, at least some of said plurality of stages each comprising storage elements for storing an instruction or decoded instruction being processed in said stage, said storage elements in at least one of said stages comprising settable elements, each of said settable elements being adapted to store a predetermined value in response to a wake up event, said settable elements being arranged such that in response to said wake up event said values stored in said settable elements form an instruction or decoded instruction.

REFERENCES:
patent: 6609209 (2003-08-01), Tiwari et al.
patent: 6665795 (2003-12-01), Roth et al.
patent: 7383426 (2008-06-01), Chung et al.
patent: 7818699 (2010-10-01), Stuber et al.
patent: 7849288 (2010-12-01), Fujisawa et al.

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