Initial-on SCR device for on-chip ESD protection

Details Initial-on SCR device for on-chip ESD protection Initial-on SCR device for on-chip ESD protection

2005-07-21

2010-11-02

Nguyen, Cuong Q (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE29216, C257SE29225, C361S056000

Reexamination Certificate

active

07825473

ABSTRACT:
A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

REFERENCES:
patent: 5576557 (1996-11-01), Ker et al.
patent: 5903420 (1999-05-01), Ham
patent: 5945713 (1999-08-01), Voldman
patent: 6011681 (2000-01-01), Ker et al.
patent: 6015992 (2000-01-01), Chatterjee et al.
patent: 6016002 (2000-01-01), Chen et al.
patent: 6097067 (2000-08-01), Ouchi et al.
patent: 6147369 (2000-11-01), Chen et al.
patent: 6465283 (2002-10-01), Chang et al.
patent: 6538266 (2003-03-01), Lee et al.
patent: 6882009 (2005-04-01), Ker et al.
patent: 7323753 (2008-01-01), Henmi et al.
patent: 2002/0122280 (2002-09-01), Ker et al.
patent: 2003/0174452 (2003-09-01), Chen et al.
patent: 2004/0042143 (2004-03-01), Ker et al.
patent: 2004/0100745 (2004-05-01), Chen et al.
patent: 2004/0100746 (2004-05-01), Chen et al.
patent: 2004/0232492 (2004-11-01), Ker et al.
patent: 2005/0133869 (2005-06-01), Ker et al.
Ker et al., “A Gate-Coupled PTLSCR/NTLSCR ESD Protection Circuit for Deep-Submicron Low-Voltage CMOS IC's”IEEE Journal of Solid-State Circuits, vol. 32, No. 1, pp. 38-51, Jan. 1997.
Ker et al. “Latchup-Free ESD Protection Design with Complementary Substrate-Triggered SCR Devices”IEEE Journal of Solid-State Circuits, vol. 38, pp. 1380-1392, 2003.
Russ et al., “GGSCR: GGNMOS Triggered Silicon Controlled Rectifiers for ESD Protection in Deep Submicron CMOS Processes”Proc. of EOS/ESD Symp., 2001, pp. 22-31.
Ker et al., “Native-NMOS-Triggered SCR (NANSCR) for ESD Protection in 0.13-μm CMOS Integrated Circuits”Proc. of IEEE Int. Reliability Physics Symp., 2004, pp. 381-386.
Ker et al., “Design of Negative Charge Pump Circuit with Polysilicon Diodes in a 0.25-μm CMOS Process”Proc. of IEEE AP-ASIC Conf., 2002, pp. 145-148.

Affiliated with

Also associated with

Rating

Initial-on SCR device for on-chip ESD protection does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Initial-on SCR device for on-chip ESD protection, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Initial-on SCR device for on-chip ESD protection will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4226970