Abrading – Precision device or process - or with condition responsive... – Computer controlled
Reexamination Certificate
2000-10-13
2003-04-01
Hail, III, Joseph J. (Department: 3723)
Abrading
Precision device or process - or with condition responsive...
Computer controlled
C451S008000, C451S287000, C451S288000, C156S922000
Reexamination Certificate
active
06540587
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the chemical mechanical planarization (CMP) of substrates, and more particularly, to techniques for end-point detection in CMP.
2. Description of the Related Art
In the fabrication of semiconductor devices, there is a need to perform CMP operations, including planarization, buffing and substrate cleaning. Typically, integrated circuit devices are in the form of multi-level structures. At the substrate level, transistor devices having diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define the desired functional device. As is well known, patterned conductive layers are insulated from other conductive layers by dielectric materials, such as silicon dioxide. At each metallization level there is a need to planarize metal or associated dielectric material. Without planarization, fabrication of additional metallization layers becomes substantially more difficult due to the higher variations in the surface topography. In other applications, metallization line patterns are formed in the dielectric material, and then metal CMP operations are performed to remove excess metallization, e.g., such as copper.
In the prior art, CMP systems typically implement belt, orbital, or brush stations in which belts, pads, or brushes are used to scrub, buff, polish and otherwise prepare a substrate. In some applications, an abrasive substance in suspension, known as slurry, is used to facilitate and enhance the CMP operation. Slurry is most usually introduced onto a moving preparation surface, e.g., belt, pad, brush, and the like, and distributed over the preparation surface as well as the surface of the substrate being buffed, polished, or otherwise prepared by the CMP process. The distribution is generally accomplished by a combination of the movement of the preparation surface, the movement of the semiconductor wafer and the friction created between the semiconductor wafer and the preparation surface.
FIG. 1A
shows a cross sectional view of a dielectric layer
102
undergoing a fabrication process that is common in constructing damascene and dual damascene interconnect metallization lines. The dielectric layer
102
has a diffusion barrier layer
104
deposited over the etch-patterned surface of the dielectric layer
102
. The diffusion barrier layer
104
, as is well known, is typically titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination of tantalum nitride (TaN) and tantalum (Ta). Once the diffusion barrier layer
104
has been deposited to the desired thickness, a metal layer, e.g., copper,
104
is formed over the diffusion barrier layer in a way that fills the etched features in the dielectric layer
102
. Some excessive diffusion barrier and metallization material is also inevitably deposited over the field areas. In order to remove these overburden materials and to define the desired interconnect metallization lines and associated vias (not shown), a metal chemical mechanical planarization (CMP) operation is performed.
As mentioned above, the metal CMP operation is designed to remove the top metallization material from over the dielectric layer
102
. For instance, as shown in
FIG. 1B
, the overburden portion of the copper layer
106
and the diffusion barrier layer
104
have been removed. As is common in CMP operations, the CMP operation must continue until all of the overburden metallization and diffusion barrier material
104
is removed from over the dielectric layer
102
. However, in order to ensure that all the diffusion barrier layer
104
is removed from over the dielectric layer
102
, there needs to be a way of monitoring the process state and the state of the wafer surface during the CMP processing. This is commonly referred to as end-point detection. In multi-step CMP operations there is a need to ascertain multiple end-points (e.g., such as to ensure that the copper (Cu) is removed from over the diffusion barrier layer; and to ensure that the diffusion barrier layer is removed from over the dielectric layer). Thus, end-point detection techniques are used to ensure that all of the desired overburden material is removed. A common problem with current end-point detection techniques is that some degree of over-processing, also known as over-polishing, is required to ensure that all of the conductive material (e.g., metallization material or diffusion barrier layer
104
) is removed from over the dielectric layer
102
to prevent inadvertent electrical interconnection between metallization lines.
One side effect of improper end-point detection or over-polishing is that dishing
108
occurs over the metal features that remain within the dielectric layer
102
. The dishing effect essentially removes more metallization material than desired and leaves a dish-like top surface over the metallization lines. Dishing is known to impact the performance of the interconnect metallization lines in a negative way, and too much dishing can cause a desired integrated circuit to fail for its intended purpose.
Dishing further contributes to a non-uniform thickness of layers in a semiconductor wafer. As is known, some circuit fabrication applications require that a specific thickness of material be maintained in order to craft a working device. By way of example, the dielectric layer
102
needs to be maintained at a specific thickness to accommodate the metallization lines and associated conductive vias defined therein.
One way of performing end-point detection is to use an optical detector. Using optical detection techniques, it is possible to ascertain a level of removal of certain films from the wafer surface. This optical detection technique is designed to detect changes in the wafer surface composition by inspecting the interference patterns received by the optical detector. Although optical end-point detection is suitable for some applications, optical end-point detection may not be adequate in cases where end-point detection is desired for different regions or zones of the semiconductor wafer.
FIG. 2A
shows a partial cross-sectional view of an exemplary semiconductor chip
201
after the top copper layer has undergone a CMP process. Using standard impurity implantation, photolithography, and etching techniques, P-type transistors and N-type transistors are fabricated into the P-type silicon substrate
200
. As shown, each transistor has a gate, source, and drain, which are fabricated into appropriate wells. The pattern of alternating P-type transistors and N-type transistors creates a complementary metal dielectric semiconductor (CMOS) device.
A first dielectric layer
202
is fabricated over the transistors and substrate
200
. Conventional photolithography, etching, and deposition techniques are used to create tungsten plugs
210
and copper lines
212
. The tungsten plugs
210
provide electrical connections between the copper lines
212
and the active features on the transistors. A second dielectric layer
204
may be fabricated over the first dielectric layer
202
and copper lines
212
. Conventional photolithography, etching, and deposition techniques are used to create copper vias
220
and copper lines
214
in the second dielectric layer
204
. The copper vias
220
provide electrical connections between the copper lines
214
in the second layer and the copper lines
212
or the tungsten plugs
210
in the first layer.
The wafer then typically undergoes a copper CMP process to remove the overburden metallization material leaving metal only in the trenches, and the entire wafer surface as flat as possible as described with reference to
FIGS. 1A-1B
. After the copper CMP process, the wafer is cleaned in a wafer cleaning system.
FIG. 2B
shows the partial cross-sectional view after the wafer has undergone optical end-point detection. As shown, the copper lines
214
on the top layer have been subjected to photo-corrosion during the detection process. T
Gotkis Yehiel
Kistler Rodney
Hail III Joseph J.
Martine & Penilla LLP
Thomas David B.
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