Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
1999-12-10
2001-08-14
Butler, Dennis M. (Department: 2182)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S501000, C713S600000
Reexamination Certificate
active
06275952
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system and an apparatus used when a CPU reads information such as hardware version information and DIP switch settings that specify a test mode when a piece of equipment is started up, and more particularly to an information transmission system and an apparatus for serially transmitting information using one clock signal line and one data signal line.
2. Background of the Invention
General-purpose field programmable gate arrays (FPGAs) have come into common use as programmable logic devices for use in computers and, while these devices feature the advantage that their operation is controllable by the circuit diagram programmed therewithin, these devices also have the problem in that it is difficult to ascertain what circuit version is operating.
For this reason, version management is an important factor when using these devices.
Although version management is commonly done by applying a physical label in the form of a seal on the device, a more reliable method is to embed the version information in the form of a circuit in the device.
It is therefore desirable that the version information be embedded using as simple a circuit and as few signal lines as possible, this applying as well to the passing of DIP switch information used to specify a test mode.
Because the above-noted type of hardware version information and DIP switch information for specifying a test mode need only be read in one time when the hardware is started up, even if the processing for reading the data is complex and requires some time to perform, it is important that the number of signal lines used be small and that this function be implemented with a simple circuit.
In the past, a common method of passing the above-noted type of information to a CPU was that of a parallel connection to a PIO (process input-output).
Another method was that of start-stop synchronized transmission of the information.
In the above-noted method of parallel connection to a PIO, however, although there is the advantage of a simple circuit configuration, there is the accompanying problem of the large number of signal lines that are required.
For example, to pass just 8 bits of information (values from 0 to 255), it is required to use 8 signal lines.
In the above-noted start-stop synchronization method, although it is only necessary to have a single signal line, the passage of even simple information required a complex circuit.
Another method is that of the electronic equipment mode setting apparatus disclosed in the Japanese Unexamined Patent Publication (KOKAI) No. 3-113522.
The above-noted mode setting apparatus has a frequency divider circuit for forming at least 3 different clocks which correspond to at least 3 different operating modes, a mode setting circuit for selecting and outputting 1 of the clocks formed by the frequency dividing circuit, and a discriminating circuit for discriminating which clock is being output by the mode setting circuit, whereby the output of the discriminating circuit is used to detect the operating mode of the equipment, thereby enabling an inexpensive simple configuration to be used in making settings of multiple modes.
The above-noted disclosure, however, does not solve the problem of achieving data transmission with a single clock, a single data line, and a simple circuit.
Accordingly, it is an object of the present invention to solve the above-noted problem, by providing an information transmission system capable of passing information using a simple circuit and few signal lines.
SUMMARY OF THE INVENTION
In order to achieve the above-noted object, the present invention has the following basic technical constitution.
Specifically, the present invention is a system and an apparatus for serially transmitting information from an information transmission section to an information receiving section, this system being provided with a single clock signal line that connects the information transmission section and the information receiving section, a clock generating section for generating a clock signal sent to said clock signal line, a first frequency dividing section for dividing said clock signal supplied from said clock generation section by a value formed by multiplying said information to be transmitted from said information transmission section to said information receiving section, by even-number, a second frequency dividing section for dividing an inverted clock derived from said clock signal by a value formed by multiplying said information to be transmitted from said information transmission section to said information receiving section, by even-number, a synthesizing section for synthesizing an XOR signal from the output signals from said first and second frequency dividing sections, and a frequency divisor detection section, disposed in said information receiving section, whereby the time interval formed between successive periods at which a level of said output signal output from said signal synthesizing section is changed at the rising edge of the clock signal, is measured, thereby detecting the value set in the first frequency dividing section, and the time interval formed between successive periods at which a level of said output signal output from said signal synthesizing section is changed at the falling edge of the clock signal, is measured, thereby detecting the value set in the second frequency dividing section.
According to the present invention, the first frequency dividing section divides the clock signal by a frequency divisor that is an even-number multiple of the information to be transmitted, the second frequency dividing section divides an inverted clock signal of that clock signal by a frequency divisor that is an odd-number multiple of the information to be transmitted.
The signal synthesizing section synthesizes a signal by taking the exclusive-OR of the output signals from the first and second frequency dividing sections, so that the signal divided by the first frequency dividing section always changes in its signal level at the rising edge of the clock signal and the signal divided by the second frequency dividing section always changes in its signal level at the falling edge of the clock signal.
Therefore, by having the frequency divisor detection section measure the time interval formed between successive period at which a level of the output signal output from the signal synthesizing section is changed at the rising edge of the clock signal, and the time interval formed between successive period at which a level of the output signal output from the signal synthesizing section is changed at the falling edges of the clock signal, it is possible to read, via the data signal line, the values which had been set in the first and second frequency dividing sections.
By doing this, it is possible to pass information via a small number of signal lines, using a simple circuit.
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Butler Dennis M.
NEC Corporation
Scully Scott Murphy & Presser
LandOfFree
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