Information storage apparatus and method for operating the same

Static information storage and retrieval – Read/write circuit – Signals

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Details

365104, 365233, 365239, G11C 700

Patent

active

058480021

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to an information storage apparatus and, in particular, an information storage apparatus for recording and reproducing binary or multi-leveled information along a time base and a method for operating the same.


BACKGROUND ART

A semiconductor storage apparatus, such as a mask ROM, is known as an information storage apparatus. This mask ROM is of such a ROM as to write information to memory cell transistors in a mask process, that is, fix "1" or "0" information, this being a so-called read-only memory.
FIG. 1 is a circuit diagram showing part of a conventional mask ROM which is structured with the use of MOS type memory cell transistors. In FIG. 1, Q1 to Q8 show MOS type memory transistors and the transistors Q1 to Q8 are connected at their gate electrodes to word lines WL1 to WL8. The transistors Q1 to Q8 are connected at their drain electrodes commonly to a bit line BL1 and grounded at their source. electrodes. Depending upon whether the MOS type transistor is of an enhancement type or a depletion type ion implanted to vary the threshold value, their fixed storage contents are made to correspond to "1" and "0". In such a structure, the transistor Q1 is made fixed to "0" and the transistor Q2 to "1", for example.
In the mask ROM thus formed, when 8-bit information or one-word information for instance is to be read out, dedicated word lines are required for the respective bits and it is, therefore, necessary to provide eight word lines in total. If, here, it is only necessary to use one word line so as to read out one-word information, then the mask ROM structure can be very much simplified.
In order to read out the one-word information of a multi-bit configuration in the conventional mask ROM it will be necessary to use word lines corresponding to the number of bits. In consequence, the mask ROM becomes complicated in configuration and it has been impossible to reduce the area of memory cells by that extent.
Although only one bit information can be recorded or reproduced with a conventional memory cell, such as one transistor, if it is possible to record and reproduce plural-bit information or multi-valued information with one memory cell, then the mask ROM can be made in highly compact form.


DISCLOSURE OF INVENTION

It is accordingly the object of the present invention to, in order to solve the above-mentioned task, provide an information storage apparatus and its operation method which can reduce the number of word lines and reduce the area of a memory cell.
In order to achieve the object of the present invention there is provided an information storage apparatus characterized by comprising: commonly to one word line; and read-out control terminals and the word line, for sequentially supplying read-out signals from the word line to the control terminals with predetermined delay times corresponding to the contents of information, wherein elements and memory elements.
Further, the present invention provides an information storage apparatus characterized by comprising: commonly to one word line; switching control terminals and the word line, for supplying read-out signals from the word line sequentially to the switching control terminals with predetermined delay times corresponding to the contents of information; and along a time base in accordance with read-out signals supplied to the delay elements, wherein delay elements and switching elements.
This invention provides a semiconductor storage apparatus characterized by comprising: plurality of series-connected resistive elements; cell transistor to a corresponding intermediate connection point between the sequentially series-connected resistive elements; and transistors along a time base in accordance with a read-out signal supplied to the word line, wherein delay circuit and memory cell transistors.
According to the information storage apparatus of the present invention, multi-bit information stored in the memory elements can be taken out continuously in a time sequence with the use of one word line and t

REFERENCES:
patent: 4488261 (1984-12-01), Ueno et al.
patent: 4495602 (1985-01-01), Sheppard
patent: 4734886 (1988-03-01), Blankenship et al.
patent: 4802121 (1989-01-01), Schreck et al.
patent: 5046045 (1991-09-01), Ebel et al.
patent: 5432744 (1995-07-01), Nagata
patent: 5596538 (1997-01-01), Joo

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