Information recording/reproducing apparatus having a clock timin

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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375376, H03D 324

Patent

active

055531040

ABSTRACT:
A clock timing extraction circuit for use in an information recording/reproducing apparatus has a phase comparator for comparing the reproduced signal with a selected clock signal to generate a phase error signal, a clock signal generation circuit for adjusting frequency to cause the error signal to approach zero according to the phase error signal and outputting a plurality of clock signals having mutually different phase differences, a selection circuit for outputting one of the plurality of clock signals on the basis of a selection signal, a phase difference judgement circuit for determining one of the plurality of clock signals having a minimum phase error (Vdet) and generating a selection signal for selection of the clock signal having the minimum phase difference, and a freeze circuit for blocking an output of the phase comparator until the clock signal having the minimum phase error is selected. The information recording/reproducing apparatus has an AGC circuit for limiting an amplitude of a reproduced signal received from a recording medium, the aforementioned clock timing extraction circuit, and a decoder circuit. The clock timing extraction circuit extracts a clock signal from an output signal of the AGC circuit and the decoder decodes the output signal of the AGC circuit on the basis of the extracted clock signal.

REFERENCES:
patent: 5022057 (1991-06-01), Nishi et al.
patent: 5034967 (1991-07-01), Cox et al.
patent: 5036528 (1991-07-01), Costantino et al.
patent: 5237590 (1993-08-01), Kazawa et al.
J. D. Coker et al, "Inplementation of PRML in a Rigid Disk Drive", IBM Storage Systems Products Division, 1991.
IEEE Transactions on Communications, May 1976, "Timing Recovery in Digital Synchronous Data Receivers", May 1976, pp. 516-531.

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