Information processor with suppressed cache coherence in low...

Electrical computers and digital processing systems: support – Computer power control – Power conservation

Reexamination Certificate

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C713S300000

Reexamination Certificate

active

10730672

ABSTRACT:
An information processor having a normal-operation mode in which coherence control is performed for making data in a cache memory of a processor identical to data in a main memory and a power-saving mode in which the coherence control is suppressed to lower the power consumption from power consumption in the normal-operation mode and entering the normal-operation mode when an input/output device accesses the main memory in the power-saving mode includes an attribute setting module for setting a device area of the main memory, accessed by the input/output device of the information processor to a non-cacheable attribute for exempting said device area from said coherence control even in the normal-operation mode; an operation mode setting module for allowing the input/output device to access the device area while keeping the operation mode of the information processor in the power-saving mode when the input/output device requests access to the device area in the power-saving mode.

REFERENCES:
patent: 4680730 (1987-07-01), Omoda et al.
patent: 5125084 (1992-06-01), Begun et al.
patent: 5157774 (1992-10-01), Culley
patent: 5210850 (1993-05-01), Kelly et al.
patent: 5481731 (1996-01-01), Conary et al.
patent: 6014751 (2000-01-01), Kardach et al.

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