Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2003-05-16
2009-06-09
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Branching
Reexamination Certificate
active
07546445
ABSTRACT:
In correspondence with an address of a branch instruction, a branch target address Apb, a valid bit V as branch history information, and delay slot information POS on the last position of delay slot instructions are stored in a branch target buffer241. A branch prediction circuit23outputs hit information H/M as to whether or not an input address Ao is coincident with the branch instruction address, the valid bit which is also a branch prediction bit, the information POS, and the branch target address Apb. When a prediction error signal ERR is inactive, the address selection circuit22selectively outputs the output of an incrementer21and the branch target address Apb, based on the hit information H/M, the delay slot information POS, and the valid bit V.
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Tago Shin-ichiro
Takebe Yoshimasa
Yamana Tomohiro
Chan Eddie P
Fujitsu Limited
Johnson Brian P
Staas & Halsey , LLP
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