Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...
Reexamination Certificate
2000-06-08
2004-03-09
Tsai, Henry W. H. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Context preserving (e.g., context swapping, checkpointing,...
C712S229000, C709S241000
Reexamination Certificate
active
06704858
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an information processor equipping a plurality of register files and to a method for switching those register files. More particularly, the present invention relates to a technique for reducing an overhead associated with an operation for switching those register files.
2. Description of the Related Art
Conventionally, an information processor equipping a plurality of register files has been well known. In this information processor, typically, a first register bank is assigned to a main routine, and a second register bank is assigned to a sub routine. When the sub routine is called from the main routine, the first register bank is switched to the second register bank. Also, when the sub routine is returned to the main routine, the second register bank is switched to the first register bank.
When the bank switching operation mentioned above is performed, in order to maintain a continuity between a process in the main routine and anther process in the sub routine, it is required that a content of a second register file constituting the second register bank for the sub routine agrees with a content of a first register file constituting the first register bank for the main routine. To accomplish this requirement, the following technique as been conventionally employed.
In a first conventional technique for the bank switching operation, such a method is employed that when the sub routine is called from the main routine, a first register bank used until that time is switched to a second register bank, and also a content of a first register file is copied to a second register file. In this case, there are a case of copying the entire content of the first register file, and a case of copying only a necessary portion of the content of the first register file. It should be noted that when the sub routine is returned to the main routine, only a process result obtained in the sub routine is returned to a particular register of the first register file by executing a special instruction immediately before this return.
FIG. 1
shows a block diagram representing a configuration of an information processor employing this first conventional technique. This information processor is composed of an instruction register
50
, an instruction decoder
51
, a first register file
52
, a second register file
53
, a selector
54
, a selector
55
, a bank switching control circuit
56
and an operation unit
57
.
The instruction register
50
transiently stores therein an instruction read out from a main memory by using an instruction fetching mechanism (not shown). A content of this instruction register
50
is sent to the instruction decoder
51
. The instruction decoder
51
extracts a register designation section in an instruction stored in the instruction register
50
, and then sends as a register address RA to the first register file
52
and the second register file
53
. This register address RA includes a read address RDA and a write address WRA.
Also, the instruction decoder
51
decodes an operation code section in the instruction, and generates a bank switch signal BK, a register transfer signal RT and an operation signal OP. The bank switch signal BK includes a signal CALL and a signal RET. The signal CALL is generated when a call instruction is set in the instruction register
50
, and the signal RET is generated when a return instruction is set in the instruction register
50
. The register transfer signal RT is generated when a register transfer instruction is set in the instruction register
50
. This register transfer instruction is used to transfer a content of the first register file
52
to the second register file
53
. Moreover, the operation signal OP is generated when instructions except the call instruction, the return instruction and the register transfer instruction, for example, various instructions such as an arithmetic operation instruction, a logical operation instruction, a comparison instruction and a movement instruction are set in the instruction register
50
.
The first register file
52
is composed of 32 registers, and is used when a main routine is executed. When the register address RA from the instruction decoder
51
is sent to the first register file
52
, a data is read out from a register specified by the read address RDA, within the first register file
52
. This read out data is sent to an input terminal A of the selector
54
and an input terminal A of the selector
55
. Also a data from the operation unit
57
is written to a register specified by the write address WRA, within the first register file
52
when the main routine is being executed.
The second register file
53
is composed of 32 registers, and is used when a sub routine is executed. When the register address RA from the instruction decoder
51
is sent to the second register file
53
, a data is read out from a register specified by the read address RDA, within the second register file
53
. This read out data is sent to an input terminal B of the selector
55
. Also the data from the operation unit
57
is written to a register specified by the write address WRA, within the second register file
53
when the sub routine is being executed.
The selector
54
selects the data from the first register file
52
entered to the input terminal A or the data from the operation unit
57
entered to the input terminal B in accordance with the register transfer signal RT sent to a select terminal S, and sends the selected data to the second register file
53
. That is, the input terminal A of the selector
54
is selected when the register transfer signal RT sent from the instruction decoder
51
is applied to the select terminal S of the selector
54
. Accordingly, the data from the first register file
52
is directly transferred to the second register file
53
through this selector
54
(the data is not transferred through the operation unit
57
). On the other hand, the input terminal B is selected when the register transfer signal RT sent from the instruction decoder
51
is not applied to the select terminal S of the selector
54
. Accordingly, the data from the operation unit
57
is transferred to the second register file
53
through this selector
54
.
The selector
55
selects any one of the data from the first register file
52
and the data from the second register file
53
in response to a control signal from the bank switching control circuit
56
, and sends the selected data to the operation unit
57
. The bank switching control circuit
56
generates the control signal to select the input terminal B of the selector
55
if receiving the signal CALL from the instruction decoder
51
and to select the input terminal A of the selector
55
if receiving the signal RET. Thus, the data from the first register file
52
is sent to the operation unit
57
during the execution of the main routine, and the data from the second register file
53
is sent to the operation unit
57
during the execution of the sub routine.
The operation unit
57
processes the data from the selector
55
, in accordance with the operation signal OP from the instruction decoder
51
. This processed result is stored in the register specified by the write address WRA, within the first register file
52
, during the execution of the main routine, and is stored in the register specified by the write address WRA, within the second register file
53
, during the execution of the sub routine.
In this information processor according to the first conventional technique, the register transfer instruction is executed immediately before the execution of the call instruction in the main routine so that the content of the first register file is copied to the second register file. As a result, the continuity between the process of the main routine and the process of the sub routine is retained.
In a second conventional technique for the bank switching operation, such a method is employed that when the sub routine is called from the main rou
Dickstein Shapiro Morin & Oshinsky LLP.
NEC Electronics Corporation
Tsai Henry W. H.
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