Information processor

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Reexamination Certificate

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Details

C714S013000

Reexamination Certificate

active

07137029

ABSTRACT:
An information processor is provided with: two chip sets that are each provided with a serial controller, these chip sets being the interface between a CPU and an input/output device; a selector for switching the connection routes between the serial controllers and the input/output device when a fault occurs in one of the chip sets; and a service processor for causing output data of the serial controller of the working chip set to be supplied to the output device and data from the input device to be supplied to each of the two serial controllers when a fault has not occurred in the chip sets, and when a fault occurs in either one of the chip sets, causing only the output data of the serial controller of the normal system to be supplied as output to the output device and data from the input device to be supplied to only the serial controller of the normal system.

REFERENCES:
patent: 5748873 (1998-05-01), Ohguro et al.
patent: 6202170 (2001-03-01), Busschbach et al.
patent: 6708287 (2004-03-01), Mitsuhashi et al.
patent: 6850807 (2005-02-01), Tahira
patent: 2006/0088121 (2006-04-01), Feher
patent: 198 14 096 (1998-03-01), None
patent: 02-094748 (1990-04-01), None
patent: 04-324535 (1992-11-01), None
patent: 06-222944 (1994-08-01), None
patent: 10-187473 (1998-07-01), None

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