Information processor

Details Information processor Information processor

1999-12-28

2003-02-04

Pan, Daniel H. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Instruction modification based on condition

C712S245000, C712S234000, C712S024000

Reexamination Certificate

active

06516407

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to an information processor, more particularly, to a VLIW processor comprising a plurality of processing units.
2. Description of the Related Art
FIG. 21
shows a relation between an instruction format of an operation with the function of a condition code generation and a schematic hardware structure for executing the instruction.
An operation code OP of the instruction is decoded, thereby a kind of operation that ALU
124
performs is determined and the following control is performed in order to perform the operation. That is, the code signals from a first source operand RS
1
and a second source operand RS
2
of the instruction, or decoded signals thereof are provided to the respective selection control inputs of selectors
125
and
126
and thereby, contents of registers selected in a general register file
161
are provided to ALU
124
. The code signal from a destination operand RD of the instruction or a decoded signal thereof is provided to the control input of a demultiplexer
127
, thereby one register in the general register file
161
is designated and an operation's result of the ALU
124
is stored into the register.
On the other hand, the code signal from an ID code CCi in the instruction, indicating a first condition code register, or a decoded signal thereof is provided to a control input of a demultiplexer
128
, thereby one of registers CC
0
to CC
7
of a first condition code register file
162
is designated and a condition code determined by the operation's result of ALU
124
is stored into the designated register. The condition code has a negative flag N, a zero flag Z, an overflow flag OV and a carry flag C. The operation is an arithmetic operation or a logic operation. A branch instruction is used to execute a branch when a condition code meets a predetermined condition.
FIG. 22
shows condition code in a branch instruction, mnemonic thereof, meaning thereof and condition to be judged. For example, when the code in the condition field is ‘0100,’ if the zero flag of the condition code is ‘1,’ then the condition is judged to be satisfied and a branch is executed, while if Z=‘0,’ then the condition is judged to be not satisfied and the branch is not executed.
In a program shown in FIG.
23
(A),
11
to
17
are instructions other than branch instruction, an unconditional branch instruction BA
7
is executed at step
3
and an unconditional branch instruction BA
9
is executed at step
7
. Therefore, instructions I
1
, I
2
, BA
7
, BA
9
and I
7
are executed in this order sequentially.
In a case where the program is run on a VLIW processor comprising a plurality of parallel processing units, each of the packets of steps
1
to
3
shown in FIG.
23
(B) is made to be one VLIW instruction by an instruction scheduler. Each instruction packet can include only one branch instruction at most, and many of NOP instructions are inserted therein, so that a parallel processing efficiency is deteriorated. In general, it is said that a branch instruction is encountered in a ratio of one in five.
In order to improve such circumstances, a proposal has been made of the predicated execution technique (“HPL PlayDoh Architecture Specification: Ver. 1.0” Vinod Kathail, Etc. HPL-93-80 February 1994, “Incorporated Guarded Execution into Existing Instruction Set” D. N. Pnevmatikatos PDH Paper Wisconsin Univ. 1996, and “The Benefit of Predicated Execution for Software Pipelining” N. J. Water, etc. HISCC-26 Conference Proceedings January 1993 Vol. 1, pp 497-606) in which no branch instruction is adopted and a conditional instruction is introduced instead.
For example in a case of FIG.
23
(A), branch instructions of steps
3
and
7
are omitted, I
3
to I
5
of steps
4
to
6
are replaced with conditional instructions C
13
to C
17
, I
6
and I
7
of steps
8
and
9
are replaced with conditional instructions C
16
and C
17
, and a program as shown in
FIG. 24
(A) is constructed. Of the conditional instructions C
13
to C
17
, only the conditional instruction C
17
is actually executed with satisfying the condition. When the program runs on a VLIW processor, only one instruction packet is needed as shown in FIG.
24
(B) and thereby, NOP instructions becomes few, which improves a parallel processing efficiency.
However, there arise the following problems in the predicated execution technique.
(1) An existing conditional branch instruction includes a condition field with a plurality of bits as shown in
FIG. 22
, and for example, when the bits is ‘0011,’ it is judged whether the exclusive OR (xor) of a negative flag N and an valid flag V thereof is ‘1’ or ‘0.’ In contrast, in the predicated execution technique, since it is judged whether or not an operation is executed depending on a value of only one flag without performing an operation between flags, another set of instructions instead of the existing one have to be adopted, thereby making existing software resources impossible to be used as they are.
(2) When the predicated execution technique is realized with a conditional instruction having a condition field of a plurality of bits such as that shown in
FIG. 22
, an instruction scheduler becomes complex, which makes the technique hard to be realized since it is decided whether or not the instruction is executed after an operation that is shown in the condition to be judged in
FIG. 22
is performed.
(3) Since a conditional instruction of the predicated execution technique focuses attention only on whether or not one condition is satisfied, a prior art conditional branch instruction also has to be employed together in a case of multiple conditions is used and NOP instructions are increased in number as described above, thereby a parallel processing efficiency is worsened.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an information processor that not only can inherit an existing instruction set architecture, but also can employ an instruction of predicated execution technique.
It is another object of the present invention to provide a information processor that can employ a conditional instruction of predicated execution technique instead of a prior art conditional branch instruction with multiple condition.
In the present invention, there is provided an information processor comprising: an instruction register for storing a fetched instruction, the instruction being one of instructions including an operational instruction with a function of generating a first condition code, a condition code conversion instruction having a reference condition code, a conditional instruction having a reference flag; an instruction decoder for decoding an instruction stored in the instruction register; a control circuit for performing a control to execute the stored instruction in response to a decoded result; a first condition code register; a second condition code register; and a condition code conversion circuit for converting contents of the first condition code register into a second condition code depending on the reference condition code, the second condition code having a condition flag, wherein the control circuit makes the generated first condition code stored into the first condition code register in response to a decoded result of the operational instruction, makes the converted second condition code stored into the second condition code register in response to a decoded result of the condition code conversion instruction, and performs a control to execute an operation of the conditional instruction in response to a decoded result of the conditional instruction only when the reference flag coincide with the condition flag in the second condition code register.
With the present invention, since not only an instruction set including a prior art operational instruction with a condition code generation function can be employed, but also a second conditional instruction that is of a predicated execution function can also be e

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