Information processing system with memory modules of a...

Details Information processing system with memory modules of a... Information processing system with memory modules of a...

2005-01-04

2005-01-04

Dang, Khanh (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus expansion or extension

C713S503000

Reexamination Certificate

active

06839786

ABSTRACT:
An information processing system for controlling clock skew preferably includes a first and a second memory module, each of which has at last one semiconductor integrated circuit and is controlled by a chipset which can selectively control the time delay of an individual clock signal based on a stored value. The system further includes a clock line, which includes a first and a second clock line segment forming a closed loop and at least one data line connected between the chipset and a first termination device. By designing each of the first and the second clock line segments to be the same length as the data line, the propagation time of a clock signal and a data signal may be accurately matched.

REFERENCES:
patent: 5243703 (1993-09-01), Farmwald et al.
patent: 6067594 (2000-05-01), Perino et al.
patent: 6393541 (2002-05-01), Fujii
patent: 6681338 (2004-01-01), Kollipara
Rambus: Enabling Maximum Performance in Desktop PCs, Rambus Inc., 1999.

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