Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-03-29
2002-01-01
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C326S047000
Reexamination Certificate
active
06336209
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an information processing system in which at least part of processing by application programs can be performed with reconfigurable programmable logic circuits. Also, the present invention relates to a circuit information management method and a circuit information storage device well-suited to the information processing system.
2. Description of the Prior Art
In the field of digital circuit elements, particularly application specific integrated circuits (ASIC), in order to reduce the development term of products, programmable logic circuits are widely used which comprise field programmable gate arrays (FPGA), programmable logic devices (PLD), and the like.
These programmable logic circuits, by loading circuit information describing logic circuits into them, permit the connections between internal logic circuits to be freely formed. Accordingly, the use of programmable logic circuits has the merit of eliminating the time for manufacturing integrated circuits, which has conventionally required from several weeks to several months after the end of circuit design. Particularly, as described in U.S. Pat. No. 4,700,187, electrically reconfigurable programmable logic circuits have the advantage of being able to be changed freely any number of times after once manufactured, so that they are being used more and more widely.
One example of a device for designing this type of programmable logic circuit is described in a patent specification entitled “Device and Method for Designing FPGA Circuits” (Japanese Published Unexamined Patent Application No. Hei 6-232259). This example, as a prior art example 1, will be described with reference to
FIGS. 28 and 29
.
FIG. 28
shows the configuration of a CAD system to design a large-sized FPGA circuit. This device has a database
12
in which a plurality of hard macro cells comprising FPGA function modules containing layout and wiring information and logic function information are cataloged, and designs a larger-sized FPGA integrated circuit by using the plurality of hard macro cells cataloged in the database for layout and wirings.
In this device, a designer operates a data input-output device
10
as a man-machine interface to run a file management program group
11
. The file management program group
11
includes a logic file management program, a library management program, a layout and wiring management program, and the like to manage the database
12
.
The database
12
comprises a logic file in which a plurality of pieces of FPGA logic function information are stored, a cell library in which FPGA cells as function modules are cataloged, and a layout and wiring file in which layout and wiring information internal to and external to FPGA is stored. In the cell library, multiple hard macro cells are cataloged which in advance have layout and wiring information and logic function information and execute specific functions as peripheral circuits and the like. The contents of each file of the database
12
are read for diagnosis from a diagnostic system
13
as required, and the diagnostic data
14
is outputted.
By sequentially using a drawing input system, a net list generation system, a layout system, an in-cell layout and wiring system, and an output program according to the contents of the files stored in the database, design drawings and a program for implementing a large-sized FPGA circuit are outputted.
FIG. 29
shows an example of the configuration of one-chip FPGA-based microcomputer system designed by the CAD system. The FPGA chip
20
comprises a CPU
21
, a ROM
22
, a RAM
23
, an I/O port
24
, a PIT (Programmable Interval Timer)
25
to measure an elapsed time of a program to be processed, a PIC (Programmable Interrupt Controller)
26
to control concurrent interrupt signals from a plurality of devices, and a DMAC (Direct Memory Access Controller)
27
to arbitrate necessary memory accesses with the CPU
21
, each of which is connected to an address/data bus
28
and a control signal line
29
.
Of these components, hard macro cells corresponding to the I/O port
24
, PIT
25
, PIC
26
, and DMAC
27
are cataloged in advance in the cell library of the database
12
and, by simply reading the hard macro cells as they are and mapping them onto the FPGA chip
20
, the hard macro cells can be laid out within the FPGA cells.
In the way described above, according to the prior art example 1, by using a library in which a plurality of hard macro cells comprising FPGA function modules having layout and wiring information and logic function information in advance are cataloged, and making layout and wirings using the plurality of hard macro cells cataloged in the library, a less heavily loaded system design can be made within a shortened development term, taking advantage of existing FPGA circuits as intellectual property.
Although the prior art example 1 described above relates to invention on the designing of one FPGA chip, recent logic circuits are increasing in complexity and their circuit scale has become large to such an extent that it cannot be achieved by one programmable logic circuit device.
As one method for solving this problem, a method is proposed which re-forms programmable logic circuits in the middle of processing to implement different logic circuits at different times. This method is advantageous in that various processing can be performed relatively quickly even in portable information terminals or the like, which are limited in the size of internal circuits because of their compact size.
However, one disadvantage of this method is that a programmable logic circuit requires much time to re-form because circuit information of the entire circuit should be read again. Moreover, re-forming in the middle of processing requires extra processing, that is, temporarily stopping processing, saving data at that time to a storage external to the programmable logic circuit, reading new circuit information for the re-forming, and inputting the data before the re-forming and new data for the re-forming. Input and output of data is redundant.
To solve this problem, a programmable logic circuit described in a data book entitled “CONFIGURABLE LOGIC” published by Atmel Corporation, a U.S. company and a programmable logic circuit described in a data book entitled “THE PROGRAMMABLE LOGIC” published by Xilinx, Inc., a U.S. company have a data storage for storing data and are partially re-formed by reading part of circuit information from the external storage even during operation of the circuits, thereby minimizing the time required for re-forming.
A problem with the use of such a programmable logic circuit in an information processing system is that re-forming into a desired logic circuit must be performed quickly and efficiently by retrieving circuit information for forming the desired logic circuit from a storing destination and synthesizing a plurality of pieces of circuit information, as required, to a format suitable for processing.
An information system that re-forms the above-described plurality of pieces of circuit information into a programmable logic circuit at different times and performs predetermined processing can be connected to a network for use. An example of this is a “reconfigurable network computer” described in Japanese Published Unexamined Patent Application No. Hei 10-78932, which will be described below as a prior art example 2 with reference to FIG.
30
.
An information processing system of the prior art example 2 comprises a plurality of computers connected to a communication network NET, at least one of which is a computer (application server) SB that distributes an application program and the remainder are client computers CL that down-load and execute the application program. Extended hardware (extended HW)
31
that can be functionally changed as required by a program and be re-formed is installed in part of the plurality of client computers CL.
The application program AP stored in the server SB, for part of functions thereo
Miyake Hiroyuki
Nakagawa Eigo
Nishihara Yoshio
Sato Yoshihide
Yamada Norikazu
Fuji Xerox Co. LTD
Smith Matthew
Speight Jibreel
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