Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Patent
1996-12-04
1997-09-09
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
711150, 711155, 395726, G06F 1214, G06F 1318
Patent
active
056665156
ABSTRACT:
Apparatus and method are provided for preventing access to a memory location while that memory location is being modified, updated, etc. When a peripheral device wishes to accomplish such a change at a memory location, it provides the changed data and its intended memory address to an input/output unit. The input/output unit includes a plurality of separately controlled multiplexers, the number of multiplexers being preferably selected to correspond to the size (in bits) of a memory data word or packet divided by the size (in bits) of a peripheral data word. The input/output unit reads the data at the requested memory location into an input buffer, combines the portions of that data not to be modified with the data provided by the peripheral, and sends the result back to the same memory location. During this Read-Modify-Write operation, the input/output unit also monitors the system bus for any attempts or requests to read data from, or write data to, the memory address for which the Read-Modify-Write operation is being performed. In such event, a signal is sent to the module making such attempt or request, asking or telling that module to wait. That signal is removed when that Read-Modify-Write operation is completed.
REFERENCES:
patent: 3108257 (1963-10-01), Buchholz
patent: 3435418 (1969-03-01), Evans et al.
patent: 3469239 (1969-09-01), Richmond et al.
patent: 3528061 (1970-09-01), Zurcher, Jr.
patent: 3528062 (1970-09-01), Lehman et al.
patent: 3573736 (1971-04-01), Schlaeppi
patent: 3706077 (1972-12-01), Mori et al.
patent: 3771146 (1973-11-01), Cotton et al.
patent: 3835260 (1974-09-01), Prescher et al.
patent: 3845425 (1974-10-01), Clements et al.
patent: 3848234 (1974-11-01), MacDonald
patent: 3848235 (1974-11-01), Lewis et al.
patent: 3848262 (1974-11-01), Belcastro
patent: 3916384 (1975-10-01), Fleming et al.
patent: 3984811 (1976-10-01), Nyssens et al.
patent: 3984814 (1976-10-01), Bailey, Jr. et al.
patent: 3984818 (1976-10-01), Gnadeberg et al.
patent: 4000485 (1976-12-01), Barlow et al.
patent: 4017840 (1977-04-01), Schild et al.
patent: 4089052 (1978-05-01), Grumer
patent: 4099243 (1978-07-01), Palumbo
patent: 4136386 (1979-01-01), Annunziata et al.
patent: 4157586 (1979-06-01), Gannon et al.
patent: 4157587 (1979-06-01), Joyce et al.
patent: 4162529 (1979-07-01), Suzuki et al.
patent: 4214304 (1980-07-01), Shimizu et al.
patent: 4394725 (1983-07-01), Bienvenu et al.
patent: 4394733 (1983-07-01), Swenson
patent: 4561051 (1985-12-01), Rodman et al.
patent: 4785394 (1988-11-01), Fischer
patent: 4858116 (1989-08-01), Gillett, Jr. et al.
patent: 4870704 (1989-09-01), Matelan et al.
patent: 4920483 (1990-04-01), Pogue et al.
patent: 4937733 (1990-06-01), Gillett, Jr. et al.
patent: 4941083 (1990-07-01), Gillett, Jr. et al.
patent: 4941182 (1990-07-01), Patel
patent: 4949239 (1990-08-01), Gillett, Jr. et al.
patent: 4975870 (1990-12-01), Knicely et al.
patent: 5016162 (1991-05-01), Epstein et al.
patent: 5067071 (1991-11-01), Schanin et al.
patent: 5068781 (1991-11-01), Gillett, Jr. et al.
patent: 5072369 (1991-12-01), Theus et al.
patent: 5088028 (1992-02-01), Theus et al.
patent: 5146588 (1992-09-01), Crater et al.
patent: 5150467 (1992-09-01), Hayes et al.
patent: 5283870 (1994-02-01), Joyce et al.
patent: 5506971 (1996-04-01), Gullette et al.
"PLUS405-55 Field-Programmable Logic Sequencer (16.times.64.times.8)" Oct. 1969, pp. 344,348 in Signetics PLD Data Handbook 1990: Programmable Logic Device (North American Philips, Jan. 1990).
Nguyen Kha
Sheth Jayesh Vrajlal
Tran Dan Trong
White Theodore Curt
Bragdon Reginald G.
Chan Eddie P.
Fassbender Charles J.
Petersen Steven R.
Starr Mark T.
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