Information processing system and memory controller for...

Details Information processing system and memory controller for... Information processing system and memory controller for...

2006-03-02

2008-11-04

Ellis, Kevin L (Department: 2187)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C711S167000, C365S230030

Reexamination Certificate

active

07447830

ABSTRACT:
An information processing system includes a plurality of memories grouped into a first memory group and a second memory group, a data processor transmitting a data access request to the memories, and a memory controller controlling data transfer between the data processor and the plurality of memories. The memory controller includes an address calculation circuit calculating a second data address from a first data address included in the data access request, and a control unit controlling operation of the first and the second memory group by transmitting a first and a second control command in different clock cycles.

REFERENCES:
patent: 6289429 (2001-09-01), Okamoto
patent: 7149841 (2006-12-01), LaBerge
patent: 2003/0088753 (2003-05-01), Ikeda et al.
patent: 2004/0024955 (2004-02-01), Patel
patent: 2004/0078512 (2004-04-01), Katayama et al.
patent: 2005/0073894 (2005-04-01), Roohparvar

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