Information processing system and cache flash control method...

Details Information processing system and cache flash control method... Information processing system and cache flash control method...

2006-05-09

2006-05-09

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C712S002000, C712S006000

Reexamination Certificate

active

07043607

ABSTRACT:
The vector unit21outputs a first flash address to the flash address array24. The vector unit31outputs a second flash address to the flash address array34. In the master unit2, the flash address array24compares an address registered in a cache with the first flash address. In the slave unit3, the flash address array34compares the address registered in the cache with the second flash address. When said first flash address coincides with said address registered in said cache, the flash address array24sends a first coincidence address to the address array25. When said second flash address coincides with said address registered in said cache, the flash address array34sends a second coincidence address to the address array25. A corresponding address of the address array25is flashed based on the first address sent from the flash address array24and based on the second address sent from the flash address34. The cache control circuit23receives an END signal from the master unit2and an END signal from the slave unit3. Thus, the flash process ends.

REFERENCES:
patent: 5123095 (1992-06-01), Papadopoulos et al.
patent: 5276848 (1994-01-01), Gallagher et al.
patent: 5418973 (1995-05-01), Ellis et al.

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