Information processing system

Details Information processing system Information processing system

2000-01-21

2001-07-24

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C713S300000, C365S227000, C365S230010, C365S210130

Reexamination Certificate

active

06266735

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an information processing system, and more particularly to an information processing system having a storage device constituted of a plurality of independently operating memory units (banks), capable of stabilizing the system operation by minimizing a change in power source current during operation and by controlling the issue of access requests.
In a system which processes technical calculations at high speed, it is important how data transfer between an arithmetic unit and a storage unit storing an immense volume of data is executed at high speed. For speeding up data transfer, a so-called cache memory mechanism has been incorporated in which frequently accessed data is registered in a high speed buffer (cache memory). This mechanism speeds up data transfer by utilizing localization of data stored in the memory unit to be accessed by a processor.
Generally, this cache memory mechanism considerably improves the system performance. However, if the scale (data amount) of each event to be processed becomes large, data overflows from the cache memory so that the performance of an arithmetic unit cannot be fully used. This data overflow can be solved if the capacity of a cache memory is large (e.g., if a memory unit having a large capacity are used or a number of memory units are used). There is a tradeoff, however, that high speed access to the cache memory becomes insufficient. High speed processing of the system cannot be expected by this approach.
In order to solve the above problem from the system architecture side, a computer system architecture independent from a cache memory has been proposed. A typical architectures is called a “vector processor scheme”. With this architecture, data is directly transferred at high speed between a main storage device and a vector register having a large capacity which holds a plurality of consecutive elements in a “column direction” or “row direction” to be used for array calculation. This architecture is disclosed, for example, in Kai Hwang, “ADVANCED COMPUTER ARCHITECTURE: Parallelism, Scalability, Programmability”, McGraw-Hill, Inc., pp. 403-414. Another example of such an architecture is a “pseudo vector processing scheme” which is disclosed, for example, in Nakamura et al “Proposal of Pseudo Vector Processor in Super Scalar Scheme and Register Window”, Parallel Processing Symposium, JSPP, 1992, Papers pp. 367-374. In this architecture, the number of registers in a standard processor is increased, and each iteration of a “DO loop” as in a FORTRAN program is processed by shifting a group of currently processing registers (a register area defined as processing registers is called a window). Namely, general registers are used by sequentially shifting a window of currently processing registers on a number of registers as if they are vector registers.
In a vector processing method such as the vector processor scheme and pseudo vector processing scheme, the types of access to a main storage device are greatly different from a computer system of a cache memory base. Namely, in the system of a cache memory base, an access to a main storage device is performed in the unit of “block” or “line” which is a registration unit of the cache memory. This size is in the range from several tens to several hundreds of bytes, and an access to the main storage device is a continuous area access. On the other hand, in the vector processing method, data of 8 bytes (in most cases, the unit of 8 bytes as double precision data is used) is transferred to and from a register. In the vector processing method, therefore, it is necessary for the main storage device side to adopt an architecture capable of accessing a large amount of data of the 8-byte unit at high speed.
In order to realize such an architecture in a vector processing system, a main storage device is generally provided with a plurality of independently operating memory units (called banks) having a 8-byte width or the like. A “bank number” is sometimes expressed as an “interleave-way number”. Although this bank number depends on a performance to be achieved by a system, there are systems having banks of several tens to several thousands.
A new factor other than the performance of a computer system is becoming an object of recent studies and developments. This factor is mainly related to low energy consumption, and a system which can realize a proper performance with a proper energy amount has been desired to be developed. With this recent development trend, CMOS LSIs are often used for high performance systems. Rapid advent of recent studies on CMOS LSIs has led to high operation speeds of CMOS LSIs with relatively low prices. This low price of LSIs constituting a computer system allows not only high-speed/high-price SRAMs but also middle-speed/low-price DRAMs to be used as memory elements of a main storage device, even in a system of the above-described “vector processing scheme”.
One problem of a main storage device of a multi-bank structure made of DRAMs is a large change in power supply current of DRAMs. Generally, because of high speed operations characteristic to SRAMs, their current consumption amount even during a non-access state (standby state) operation does not change greatly from that during an access state (operation state).
In contrast, the current consumption amount of DRAM changes greatly between the non-access state and access state. In some cases, the current amount may change by about three digits. A large change in the current amount between both the states poses one problem. This problem lies in the main storage access characteristics specific to the “vector processing scheme”, namely an abrupt change from a preparatory stage before vector processing with less accesses to the main storage to a stage during vector processing with frequent accesses to the main storage. Such a quick rise of accesses in the “vector processing scheme” causes a number of banks to change at the same time from the non-access state to the access state. A power supply current to DRAMs therefore increases abruptly. For example, a power supply current to one DRAM is about 100 mA in the access state. If the operation states of DRAMs of several hundreds to several thousands change at the same time, a power supply current of several tens to several hundreds of ampere is supplied to the main storage device. This becomes a critical issue of a power supply system of the main storage device, because this system cannot respond at once to such an instantaneous large current change. Generally, a load change response characteristics of a power source relative to electronic circuits are in the order of &mgr;s at the faster level. This time is determined depending upon inductance and resistance components in the circuit path from the power source to the electronic circuits.
A relationship between a power source, a power supply system and an electronic circuit group is illustrated in
FIG. 12
by using a model of the power supply system. In
FIG. 12
, current is supplied from a power source
1101
to an electronic circuit group such as an LSI
1104
and a DRAM
1105
via a mother board
1102
and a package
1103
. An equivalent circuit of the power supply system is represented by inductance components
1110
,
1113
and
1116
and resistance components
1111
,
1114
and
1117
which are connected in series with the electronic circuit group, and by capacitance components
1112
and
1115
or the like which are connected in parallel to the electronic circuit group.
If the power supply system has a narrow wiring pattern and has large inductance components, the response time prolongs. During a response period, the amount of current supplied via the power supply system becomes insufficient so that in a simple case, the voltage applied to the electronic circuit group lowers. A general countermeasure for dealing with a temporary change in the current amount to be caused by a load change, is to replace the capacitors
1112
and
1115
shown in
FIG. 12
by capacitors

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