1996-07-03
1998-11-10
Beausoliel, Jr., Robert W.
39518307, G06F 1100
Patent
active
058356975
ABSTRACT:
A TMR unit connects a plurality of processors by a bus and simultaneously executes the same processing operation. Among the plurality of processors, one of them is a master and the remaining processors are slaves. Information formed by only the master processor is outputted to the bus. Each processor has a multiplex control circuit. The multiplex control circuit compares output information formed by itself with bus information outputted to the bus, thereby detecting a failure and allowing an internal circuit to execute necessary processes.
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Hirose Yoshio
Katoh Shinya
Kishino Takumi
Noda Takato
Nonomura Kazuhiro
Beausoliel, Jr. Robert W.
Fujitsu Limited
Iqbal Nadeem
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