Information processing system

Details Information processing system Information processing system

1997-09-19

2000-09-12

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

713300, 365227, 36523003, G11C 800

Patent

active

06119199&

ABSTRACT:
In an information processing system, a main storage access request issued from a processor is input to an access buffer mechanism provided in a memory control device, and sent via an operation request issue control mechanism to a main storage device constituted of a plurality of memory units (banks). In the memory control device, the operation status of each bank constituting the main storage device is managed and the number of banks under operation is counted. The predetermined number (operation bank limit number) of banks required to operate at a minimum is compared with the number (operation bank number) of banks under operation. If the operation bank number is smaller than the operation bank limit number, the memory control device instructs a dummy operation request generation mechanism to generate a dummy operation request, in order to prevent a large change in a power supply current to be caused by an abrupt change in the number of access requests to the main storage device and to realize a system stable operation. A dummy operation request generation mechanism determines a bank which executes a dummy operation, and an operation request issue control mechanism issues a dummy operation request to the determined bank in the main storage device.

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Kai Hwang, "Advanced Computer Architecture: Parallelism, Scalability, Programmability", McGraw-Hill, Inc., pp. 403-414.
Nakamura et al., "Proposal of Pseudo Vector Processor in Super Scale Scheme and Register Window", Parallel Processing Symposium, JSPP, 1992, Papers pp. 367-374.

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