Electrical computers and digital data processing systems: input/ – Interrupt processing – Handling vector
Reexamination Certificate
1999-02-03
2001-07-31
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Interrupt processing
Handling vector
C710S260000, C710S264000
Reexamination Certificate
active
06269419
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an information processing method and an information processing apparatus. More specifically, the present invention is directed to an interrupt control method, and an interrupt control apparatus controlling a plurality of interrupt requests by applying priority orders, or priority degrees to these interrupt requests.
2. Description of the Related Art
When an interrupt process occurs while a main process operation is executed by a processor, this processor temporarily interrupts the main process operation under execution, and executes the interrupt process. In the case that such interrupts are produced in a multiple manner, since the processor cannot simultaneously execute a plurality of interrupts, the processor is required to perform an interrupt control in such a manner that the processor applies priority orders, or priority degrees to these plural interrupts, and then sequentially executes the interrupt processes having the higher priority orders.
A typical interrupt process operation executed by one conventional information processing apparatus is described as follows:
FIG. 9
is a schematic block diagram for representing an arrangement of a conventional interrupt control apparatus.
FIG. 10
is a timing chart for explaining a control operation executed by this conventional interrupt control apparatus.
FIG. 11
is a state transition diagram for indicating state changes in the respective structural arrangement units of this conventional interrupt control apparatus.
As indicated in
FIG. 9
, the conventional interrupt control apparatus is mainly arranged by an interrupt flag holding circuit
11
, an interrupt level holding circuit
12
, an interrupt level judging circuit
13
, an interrupt factor holding circuit
14
, an interrupt vector generating circuit
15
, and an interrupt vector holding circuit
16
. When an interrupt request is entered, the interrupt flag holding circuit
11
sets a flag in correspondence with the entered interrupt request, and further holds an interrupt level. The interrupt level holding circuit
12
holds an interrupt level of an interrupt request under execution by a processor. The interrupt level judging circuit
13
judges such an interrupt level having a top priority order among the interrupt levels held in the interrupt flag holding circuit
11
, and outputs an interrupt factor corresponding thereto. The interrupt factor holding circuit
14
holds the interrupt factor outputted from the interrupt level judging circuit
13
. The interrupt vector generating circuit
15
generates such an interrupt vector indicative of an interrupt sort in response to the interrupt factor outputted from the interrupt level judging circuit
13
. The interrupt vector holding circuit
16
holds the generated interrupt vector, and outputs the held interrupt vector to the processor
17
.
Next, the interrupt processing operation executed in the above-explained conventional information processing apparatus will be described with reference to
FIG. 9
to FIG.
11
. Since this interrupt processing operation is sequentially advanced every 1 cycle of a clock CLK, state changes of the respective circuits will be explained as to interrupt processing operations for 19 cycles. In the drawings, an IF stage (interrupt flag holding stage) indicates an operation cycle of the interrupt flag holding circuit
11
; a PRI stage (interrupt level judging stage) shows an operation cycle of the interrupt level judging circuit
13
; a VCT stage (interrupt vector generating stage) represents an operation cycle of the interrupt vector generating circuit
15
; and an EXT cycle (interrupt vector output stage) denotes an operation cycle of the interrupt vector holding circuit
16
. It should be understood that symbols “pri
0
” to “pri
7
” show interrupt priority orders (degrees), and a relationship among these interrupt priority orders is defined by as follows:
pri
0
>pri
1
>pri
2
>pri
3
>pri
4
>pri
5
>pri
6
>pri
7
The interrupt processing operations of the conventional information processing apparatus are executed in accordance with the following cycles:
(1) 1st Cycle
Assuming now that an interrupt request having a priority order “pri
7
” is issued in any one of interrupt request inputs INT-
0
to INT-x under such a condition that all of the contents of the interrupt flag holding circuit
11
and of the interrupt level holding circuit
12
are cleared, a flag is set to the interrupt flag holding circuit
11
in the IF stage (this state is indicated as “IF
7
”).
(2) 2nd Cycle
Next, in the PRI stage, the interrupt level held in the interrupt flag holding circuit
11
is read, and the read interrupt level is judged by the interrupt level judging circuit
13
. At such a present time when only one interrupt request is issued, since the priority order pri
7
is the highest order, the interrupt factor of pri
7
is held in the interrupt factor holding circuit
14
, and also an interrupt request “REQ” based upon pri
7
is outputted to the processor
17
from the interrupt level judging circuit
13
via an interrupt request signal line INTRQ (this state is indicated as “PRI
7
”). At this time, since an interrupt request having a priority order “pri
6
” is issued, a flag is set to the interrupt flag holding circuit
11
in the IF stage (this state is indicated as “IF
6
”).
(3) 3rd Cycle
While the interrupt request REQ based on pri
7
is issued from the interrupt level judging circuit
13
to the processor
17
, this processor
17
is set to such a state for rejecting the interrupt request REQ based on pri
7
. At this time, at a VCT stage, the interrupt vector generating circuit
15
generates an interrupt vector by the interrupt factor read from the interrupt factor holding circuit
14
, and the generated interrupt vector of pri
7
is held in the interrupt vector holding circuit
16
(this state is indicated as “VCT
7
”). Also, in the IF stage, since an interrupt request having a priority order of “pri
5
” is issued, a flag is set to the interrupt flag holding circuit
11
(this state is indicated as “IF
5
”).
(4) 4th Cycle
Subsequently, while the interrupt request REQ based on pri
7
is issued from the interrupt level judging circuit
13
to the processor
17
, this processor
17
is set to such a state for rejecting the interrupt request REQ based on pri
7
. At this time, at an EXT stage, the interrupt vector based upon pri
7
held in the interrupt vector holding circuit
16
is read to an interrupt vector signal line INTLV (this state is indicated as “EXT
7
”). Also, in the IF stage, since an interrupt request having a priority order of “pri
4
” is issued, a flag is set to the interrupt flag holding circuit
11
(this state is indicated as “IF
4
”).
(5) 5th Cycle
Subsequently, the interrupt request REQ based upon pri
7
is outputted from the interrupt level judging circuit
13
, and further an interrupt vector based on pri
7
held in the interrupt vector holding circuit
16
is read. Since the processor
17
is capable of executing an interrupt process operation, this processor
17
can accept an interrupt request REQ with respect to this interrupt. At this time, since the interrupt request based upon the priority order of “pri
1
” is issued, a flag is set to the interrupt flag holding circuit
11
in the IF stage (this state is indicated as “IF
1
”).
(6) 6th Cycle
Subsequently, the interrupt request REQ based upon pri
7
is outputted from the interrupt level judging circuit
13
, and also the interrupt vector bases on pri
7
held in the interrupt vector holding circuit
16
is read. The processor
17
samples the interrupt vector based on pri
7
to branch the sampled interrupt vector to a target. The processor
17
commences an interrupt service of pri
7
by performing an interrupt process operation in an interrupt process routine, and further returns an interrupt acknowledge AK to the interrupt flag holding circuit
11
via an interrupt acknowledge signal line INTAK. As a result, the
Foley & Lardner
NEC Corporation
Ray Gopal C.
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