Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-12-27
2004-01-06
Thai, Xuan (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C713S400000
Reexamination Certificate
active
06675249
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to input/output to/from a microprocessor system, particularly to a technique of controlling the frequency conversion for clock frequency matching between a processor and its peripherals such as an L
2
cache and an external bus that operate, based on a clock frequency different from the clock frequency for processor operation.
Processors used in the field of information processing systems and control equipment are required to have more increased performance with a higher processing rate, causing the operating clock frequency of processors to become higher. On the other hand, peripherals such as L
2
caches, memory controllers, external buses, and network adapters, operate at a lower frequency because of cost reduction and energy saving. In multiprocessor systems, the communication rate between processors depends on the communication path wiring delay and this limits the clock frequency for bus operation. It is thus important to support a lower clock frequency for bus operation than the clock frequency for processor operation.
Japanese Patent Prepublication (J-P-A) No. Hei 7-210267 (its U.S. version is U.S. Pat. No. 5,485,602) disclosed a method that a single clock that is externally input is used as an internal clock. If this method is applied to a system comprising many interconnected units such as a multiprocessor system, however, clock skew is a problem when synchronizing the units.
As described in J-P-A No. Hei 5-233275, another method is known that as many clocks as the required number of clock lines are generated, each clock being at a fixed frequency and a given phase to other clocks. This is accomplished by PLL circuits and a higher frequency clock is used as the clock for a processor and a lower frequency clock is used for a bus I/O signal conversion circuit that interfaces with an external bus. In order to synchronize the internal and external components of a processing equipment or system, each operating, based on one of a plurality of clocks of different frequencies, schemes of supplying different clocks by using PLL have been developed. Examples of these schemes are given below.
A first one is a multiple PLLs scheme is such that as many independent PLLs as the number of clock supply lines are prepared as will be shown in FIG.
2
. Because each clock line has its feedback in this scheme, phase matching is possible even if the clock supply lines are used to supply different clocks.
A second one is a multiple dividers scheme is such that only a single PLL is used and as many dividers as the number of clock supply lines are connected to its voltage control oscillator (VCO) to supply different clocks as will be shown in FIG.
3
. The second scheme can avoid the interference between the PLLs that is a problem of the multiple PLLs scheme.
If a plurality of clock lines are wired on a chip to supply an internal clock, a clock for L
2
cache interface, and a clock for external bus interface, according to the above schemes, the phase matching of different clock lines involves the following problems.
For the multiple PLLs scheme, because each clock line has its feedback as will be shown in
FIG. 2
, any clock skew can be adjusted to the internal clock. However, the clock for L
2
cache interface and the clock for external bus interface have a smaller rate of FF to drive than the internal clock, but theses clock supply lines extend over the chip because of I/O-related circuits and need to be wired in the same method for supplying the internal clock. Thus, the wiring area is (the wiring area for internal clock) multiplied by (the number of clock lines) and the consumed power increases proportionally. In addition, the problem of interference between PLLs makes the wiring of the PLLs difficult.
For the multiple dividers scheme, because of the single PLL as will be shown in
FIG. 3
, the interference problem is eliminated. However, the feedback control of PLL is provided for only one of all clock lines and therefore the phase matching for the remaining clock lines must be performed without feedback. Consequently, all clock supply lines need to be designed equally and wired as is for the internal clock supply circuit, similar to the first scheme, and this increases the wiring area and consumed power.
SUMMARY OF THE INVENTION
Objects of the present invention is supplying only a reference clock to internal and external components of information processing equipment so that the components will be synchronized easily and performing frequency conversion control for frequency matching between a plurality of clocks only in a logical circuit by using clock pulses generated from the reference clock in order to solve the above problems. The invention is also intended to provide a bus interface controller and processing equipment on which the bus interface controller is installed. The bus interface controller performs frequency conversion control for clock frequency matching between internal and external clocks, especially when the internal-to-external clock frequency ratio is N:1 or N:2, only in a logical circuit with only an internal clock supply line instead of wiring a plurality of clock lines, such that the processor and peripherals can be synchronized easily and clock supply wiring can be performed with smaller wiring area and lower power consumption.
The bus interface controller offered by the present invention needs only the reference clock to synchronize the internal and external components of the processing equipment or system and includes a means to generate a reference sync signal for synchronizing the components and an internally operating clock of the equipment from the reference clock. The bus interface controller also includes a synchronous counter that determines the number of counts in accordance with a preset clock frequency ratio and is reset by the above reference sync signal. The bus interface controller also includes a means to generate timing signals for access to peripheral equipment by the comparison between the preset clock frequency ratio and the synchronous counter. The bus interface controller also includes a means to perform frequency conversion control of input/output signals to/from another processor, peripheral equipment, or bus only in a logical circuit, supplied with the internally operating clock across only a single line as the clock on which the equipment operates and by using the access timing signals as enable signals to be applied to latches for external interface control that are activated by an enable signal. The bus interface controller also includes a function of accessing another processor, peripheral equipment, or bus that operates at a rate of 2/N [where N≧2] (1, 1/1.5, 1/2, 1/2.5, 1/3, . . . ) of the internally operating clock frequency by using clock pulses of 50% duty as the internal clock. The bus interface controller also includes a function of accessing another processor, peripheral equipment, or bus that operates at a rate of M/N [where N≧M≧2] of the internally operating clock frequency by using M-phase clock pulses with each in phase shifted by 1/M cycle or clock pulses of 50% duty with a frequency that is M/2 times the frequency of the internal clock.
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patent: 5-233275 (1993-09-01), None
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Shimoda Teruaki
Yamagata Ryo
Yamamoto Kei
Thai Xuan
Townsend and Townsend / and Crew LLP
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