Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2004-09-10
2010-12-14
Choe, Yong (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S141000, C711S163000, C712S216000, C712S233000, C714S763000
Reexamination Certificate
active
07853756
ABSTRACT:
In a method for controlling a processor which accesses information of a storage device through cache memory, when reading information stored in a target address or an address range of the storage device, it is monitored whether there is an update access to the address or address range from another processor, and also the processor is entered into a suspense status, which is released using the occurrence of the update access to the storage device from another processor as a trigger.
REFERENCES:
patent: 4513367 (1985-04-01), Chan et al.
patent: 4780843 (1988-10-01), Tietjen
patent: 5623629 (1997-04-01), Suzuki
patent: 6189088 (2001-02-01), Gschwind
patent: 6493741 (2002-12-01), Emer et al.
patent: 6802039 (2004-10-01), Quach et al.
patent: 6836824 (2004-12-01), Mirov et al.
patent: 6986015 (2006-01-01), Testardi
patent: 2002/0013872 (2002-01-01), Yamada
patent: 2003/0033510 (2003-02-01), Dice
patent: 2003/0126186 (2003-07-01), Rodgers et al.
patent: 2003/0126375 (2003-07-01), Hill et al.
patent: 2004/0128456 (2004-07-01), Kobayashi et al.
patent: 2004/0210723 (2004-10-01), Naruse et al.
patent: 2005/0187939 (2005-08-01), Krithivas
patent: 57-158081 (1985-09-01), None
patent: 61-229150 (1986-10-01), None
patent: 3-81859 (1991-04-01), None
patent: 3-164964 (1991-07-01), None
patent: 05-127996 (1993-05-01), None
patent: 5-225149 (1993-09-01), None
patent: 11-282815 (1999-10-01), None
patent: 2002-41489 (2002-02-01), None
patent: 2006-500639 (2006-01-01), None
patent: 03/040948 (2003-05-01), None
patent: 03/058447 (2003-07-01), None
The SPARC Architecture Manual Version 9 J Programming with the Memory Models (with a note; this appendix is informative only. It is not part of the SPARC-V9 specification.) (SPARC Int'l Inc.) ISBN 0-13-25001-4 pp. 323-338.
“System/370 Principles of Operation” (IBM) SA22-7832-00 pp. 4-5˜4-6.
“Intel Architecture Software Developers Manual vol. 2” (intel) Instruction Set Reference p. 3-291.
European Search Report issued in corresponding European Application No. 04225531.8, on Aug. 3, 2007.
Japanese Office Action mailed on Jun. 16, 2009 in corresponding Japanese Patent Application 2004-135875 (3 pages) (3 pages English translation).
English Patent Abstracts of Japan, Japanese Publication No. 10-124316, Published May 15, 1998.
English Patent Abstract of Japan, Japanese Publication No. 2001-236226, Published Aug. 31, 2001.
Japanese Office Action mailed Mar. 3, 2009 in corresponding Japanese Patent Application 2004-135875 (3 pages) (2 pages English Translation).
Choe Yong
Fujitsu Limited
Staas & Halsey , LLP
LandOfFree
Information processing device, processor, processor control... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Information processing device, processor, processor control..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Information processing device, processor, processor control... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4173450