Electrical computers and digital data processing systems: input/ – Interrupt processing – Multimode interrupt processing
Reexamination Certificate
2000-03-22
2003-03-18
Dharia, Rupal (Department: 2181)
Electrical computers and digital data processing systems: input/
Interrupt processing
Multimode interrupt processing
C370S223000
Reexamination Certificate
active
06535943
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an information processing device comprising a plurality of CPUs, and more particularly, to an information processing device which immediately executes an interrupt condition change instruction if no pending floating interrupt as an interrupt that can be executed by any of the plurality of CPUs exists.
2. Description of the Related Art
In an information processing device comprising a plurality of CPUs, there are various methods in the case where one or the plurality of CPUs are made to execute interrupt processing. For example, the case where a particular CPU is specified and made to execute interrupt processing, the case of a broadcast interrupt that makes all of the CPUs execute interrupt processing, the case of a floating interrupt (an event-like interrupt) that may make any of the plurality of CPUs execute interrupt processing, or the like. The present invention targets an information processing device which makes the above described floating interrupt pending.
Normally, interrupt processing is not immediately executed in all cases, and its execution is sometimes made pending. Assume that one of a plurality of CPUs decodes an interrupt condition change instruction within a program, and this instruction is attempted to be executed. This interrupt condition change instruction is, for example, an instruction which changes an interrupt enable mask to be described later.
Normally, when this interrupt condition change instruction is executed, whether or not an interrupt to be processed under a current interrupt condition is pending is examined within an information processing device. If the interrupt to be processed is pending, this instruction is executed after the interrupt processing is executed. If the interrupt to be processed is not pending, the instruction is immediately executed.
A conventional method for processing such a pending floating interrupt will be described below by taking an input/output interrupt as an example of a floating interrupt.
FIG. 1
is a block diagram showing the fundamental configuration of an information processing device for an explanation of pending input/output interrupt processing. In this figure, the information processing device comprises an IOP (Input/Output Processor)
50
, an MCU (Memory Control Unit) controlling a storage device such as a main storage, etc., and a plurality of CPUs (Central Processing Units)
52
0
to
52
n
. The CPUs
52
0
to
52
n
respectively include instruction controlling units
53
0
to
53
n
controlling instructions within the respective CPUs.
In
FIG. 1
, an input/output interrupt, for example, an interrupt corresponding to each of a plurality of input/output channels is transmitted from the IOP
50
to the MCU
51
as a floating interrupt, for example, along with the signal indicating that the interrupt is pending. Within the MCU
51
, data indicating whether or not a floating interrupt is pending is stored in correspondence with each of the channels in a pending latch to be described later.
An interrupt condition change instruction changing an interrupt condition is decoded, for example, by one of the plurality of CPUs
52
0
to
52
n
, and the need for executing this instruction arises. A floating interrupt may be executed by any of the CPUs as described above. Therefore, each of the instruction controlling units
53
0
to
53
n
within each of the CPUs transmits to the MCU
51
an interrupt enable mask stored therein, that is, the value of the mask indicating whether or not an interrupt is enabled for its CPU in correspondence with each of the input/output channels.
Since the interrupt enable mask and the above described pending latch store the data corresponding to each of the channels one by one, the MCU transmits an interrupt processing request signal (trigger signal) to the instruction controlling unit within the CPU whose mask value of the input/output channel corresponding to the pending interrupt is, for example, 1, and whose priority is the highest. The CPU controlled by the instruction controlling unit starts the interrupt processing upon receipt of the trigger signal.
FIG. 2
is a flowchart showing a conventional interrupt condition change instruction process. Once the process is started in this figure, an interrupt condition change instruction is first decoded, for example, by a certain CPU in step S
10
and the need for executing this instruction arises. Then, an interrupt enable mask is transmitted from the instruction controlling unit in each of the CPUs to the MCU in step S
11
. If a pending floating interrupt exists, the process for selecting a CPU made to execute this interrupt and for transmitting a trigger signal to the selected CPU is started prior to the execution of the interrupt condition change instruction on the MCU side.
In the instruction controlling unit in each of the CPUs, a counter, for example, a process wait counter to be described later, is started in order to wait for a trigger signal which can possibly be transmitted from the MCU side, when the interrupt enable mask is transmitted in step S
11
, and whether or not the counter times out is determined in step S
12
. If the counter does not time out, whether or not the trigger signal is reached is determined in step S
13
. If the trigger signal is not reached, the operations in and after step S
12
are repeated.
If the trigger signal is determined to be reached in step S
13
before the counter does not time out in step S
12
, the pending interrupt is processed by the CPU which has received the trigger signal, that is, the selected CPU. In the unselected CPUs, the interrupt condition change instruction in step S
15
is executed when the counter is determined to time out in step S
12
, and, for example, the interrupt enable mask stored in the instruction controlling unit is rewritten.
FIG. 3
is a block diagram showing the configuration of the information processing device in which the configuration of the MCU is especially illustrated in detail. Processing for a pending floating interrupt in this figure will be explained below. In this figure, an IO rupture (RUPT) ID (7 bits+parity check bit P) signal (+IO_RUPT_ID) indicating to which one of for example, 128 input/output channels an interrupt corresponds is transmitted from the IOP
50
to the MCU
51
along with a signal (+SET_PENDING) making an IO (Input/Output) interrupt pending in (
1
). These values are once stored in a 10-bit latch
70
. Then, the value of the IO rupture ID by a decoder
71
, and the bit corresponding to the input/output channel for which an interrupt is made pending is assumed to be “1” among four pending latches
72
1
to
72
4
of 32 bits respectively corresponding to the 128 channels in (
2
).
When one CPU decodes an interrupt condition change instruction and the need for executing the decoded instruction arises, the contents (128 bits) of the IO rupture masks
79
0
to
79
15
indicating whether or not an interrupt corresponding to the respective input/output channels is enabled are serially transferred, for example, by 4 bits in 32 time divisions by the instruction controlling unit within each of the CPUs. This serial transfer is not limited particularly to 32 time divisions.
A priority circuit
75
, which selects the CPU made to process a pending floating interrupt as described above within the MCU
51
, makes a comparison between the interrupt enable mask transmitted from the CPU side and the contents stored in the pending latches, and determines whether or not an interrupt by each of the CPUs is enabled for the pending floating interrupt. Accordingly, the contents stored in the respective pending latches
72
1
to
72
4
are serially transferred to the priority circuit
75
via selectors
73
1
to
73
4
according to the selection control of a mask select counter. Here, the mask select counter is a counter for this time division transfer, and does not always mean a mask selection.
The priority circuit
75
makes a comparison between the conte
Hatamori Syuuei
Inoue Aiichiro
Dharia Rupal
Fujitsu Limited
Staas & Halsey , LLP
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