Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1999-12-14
2002-08-20
Hudspeth, David (Department: 2651)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S003000, C711S168000
Reexamination Certificate
active
06438662
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an information processing device comprising a microprocessor having a cache memory.
In recent years, according to gradual increase of processing speed of a microprocessor, the information processing device, in which a cache memory is installed inside the microprocessor to realize a high speed processing of memory access, has been popularized. In such information processing device a program data and a part of other data stored in the memory (main memory, herewith) installed outside microprocessor are stored in the cache memory inside the microprocessor and the microprocessor accesses the cache memory by replacing to the main memory access to allow getting data from the memory with a high speed.
Meanwhile, in such information processing device, when the outside device operates direct memory access (DMA), for example, by a bus master function to renew the contents of the main memory by the outside device, data held by the cache memory inside the microprocessor and data held by the main memory do not correspond each other. Therefore, after DMA by the outside device, the contents of all the cache memory are once cleared together with the program data and other data.
As the result, for a short time after DMA, the microprocessor gets data from not the cache memory, but the main memory to need tome of memory access resulting in processing performance of the microprocessor.
Then, in order to solve this problem, for example, unexamined Japanese Patent Publication Sho62-145445, namely, No.145445/1987, discloses a method in which management is operated by dividing the cache memory into data area and code area and according to situation, only one area, for example the data area is cleared to keep a certain hit rate of the cache memory, even after DMA has been operated.
However, in this method the cache memory is divided into small areas to cause that data are stored in entire area in the one area, but data are stored in a part of the other area. Thus, the following problem occurs: as a whole, the cache memory cannot be effectively used.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an information processing device allowing the maximum processing performance for the microprocessor by making possible the effective application of the cache memory, even after the outside device directly accessed the main memory.
Other objects of the present invention will become clear as the description proceeds.
In order to accomplish the above object, the present invention provides an information processing device comprising a microprocessor containing a cache memory, a main memory installed in the outside of said microprocessor to be accessed by said microprocessor, and an outside device to access directly said main memory, wherein said microprocessor comprises the first address storage means to store an address of said main memory to be accessed by said microprocessor, the second address storage means to store the address of said main memory to be accessed by said outside device, a controlling means of address storage to make the second address storage means store by getting the address, to which said outside device accesses, from said outside device, when said outside device accesses said main memory, a controlling means of access memory compares addresses stored by said first and second address storage means when said microprocessor reads a datum from said main memory, if the two addresses differ each other, makes said microprocessor access said cache memory and if the two addresses are identical, makes said microprocessor access said main memory.
In information processing device of the present invention, the controlling means of address storage gets an address, which the outside device accesses, from the outside device to make the second address storage means store, when the outside device accesses the main memory. The access memory controlling means compares addresses stored by the first and the second address storage means, when the microprocessor reads data from the memory. If the two addresses differ each other, make said microprocessor access said cache memory. On the other hand, if said two addresses are identical, make said microprocessor access said main memory.
Therefore, as the result of renewal of stored contents by accessing of the main memory by the outside memory, even if stored contents of the cache memory differs from those of the main memory, when the microprocessor reads data from the address, the microprocessor is automatically controlled to read data from the main memory and not from the cache memory.
Therefore, in the information processing device of the present invention, the maximum processing performance is realized for the microprocessor by making possible the effective application of the cache memory without conventional clearing of the cache memory, even after the outside device renewed the stored contents of the main memory.
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Hayashi Hiroshi
Nagatani Mamoru
Foley & Lardner
Hudspeth David
NEC Corporation
Tzeng Fred F.
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