Information processing device and processor

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique

Reexamination Certificate

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Details

C710S110000

Reexamination Certificate

active

07404054

ABSTRACT:
A device with a small number of circuits is provided for blocking illegal address access from a bus master device connected to the processor system bus. An illegal address blocking circuit is inserted into the address line and control lines between the bus master device and the bus or the bus control circuit, according to the system bus configuration. A register is installed within the illegal address access blocking device to set an address range where access is allowed. The address output from the address line is then checked by a comparator to find if it is within the allowable range or not, and if it is outside the allowable range, then that illegal access is prevented by blocking the output on the control line.

REFERENCES:
patent: 6311255 (2001-10-01), Sadana
patent: 6519690 (2003-02-01), Quimby
patent: 6701397 (2004-03-01), Foster et al.
patent: 2002/0062414 (2002-05-01), Hofmann et al.
patent: 2004/0103230 (2004-05-01), Emerson et al.

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