Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output command process
Patent
1997-05-20
2000-06-20
Lee, Thomas C.
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output command process
710 48, 710260, G06F 930
Patent
active
060789697
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to an information processing device and an information processing method for performing sequence processing such as programmable logic controller (which will be referred to as "PLC" hereinafter) as well as information processing, and in particular relates to a device and a method for information processing, which allow inexpensive construction of a whole system using a general-purpose computer, and also allow information processing with a minimum influence exerted on a cycle of the sequence processing.
BACKGROUND ART
Such information processing devices have recently been proposed that perform sequence processing of a PLC or the like utilizing a general-purpose personal computer, and also perform information processing. These information processing devices utilizing general-purpose personal computers can be classified into the followings:
(1) A type in which a PLC board is connected to a slot of a general-purpose computer (which will be referred to as a "board PLC").
(2) A type in which a general-purpose personal computer is added to a PLC (which will be referred to as a "PLC+personal computer"), and
(3) A type in which an intended function is provided by software on a general-purpose personal computer (which will be referred to as a "software PLC").
FIG. 16 is a block diagram showing a schematic structure of the board PLC. Board PLC 15 has a structure in which a PLC board 20 is connected to a slot of a general-purpose personal computer 10 (which will be simply referred to as a "personal computer" hereinafter) through a personal computer expansion bus 30.
Personal computer 10 includes a microprocessor unit (MPU1) 11 and a work memory 12.
PLC board 20 includes a ladder interpreter 21, a memory 22, a microprocessor unit (MPU2) 23, a read-only memory (ROM) 24 and a buffer 25.
Memory 22 includes a user memory UM for storing a ladder program which is a user program, and an input/output memory IOM for storing input/output information.
In the above structure, ladder interpreter 21 has a function as a bus controller, so that microprocessor unit (MPU1) 11 of personal computer 10 can access memory 22 of PLC board 20 through personal computer expansion bus 30. ladder interpreter 21 can access work memory 12 of personal computer 10 through personal computer expansion bus 30.
The processing of PLC can be basically classified into two kinds of processing, i.e., "instruction execution" for interpreting and executing a ladder program and "peripheral processing" for performing input refreshing (IN-refreshing) and output refreshing (OUT-refreshing) of an input/output port (I/O) and others.
In the board PLC shown in FIG. 16, the ladder interpreter 21 fetches and decodes a ladder program stored in user memory UM of memory 22 for the above "instruction execution".
Read-only memory (ROM) 24 in PLC board 20 has stored a peripheral processing program for the foregoing "peripheral processing". Microprocessor unit (MPU2) 23 executes the "peripheral processing" using the peripheral processing program stored in read-only memory (ROM) 24.
In the foregoing structure, personal computer 10 uses work memory 12 for executing predetermined information processing.
The "PLC+personal computer" described above differs from the above board PLC in that the PLC is not formed of a PLC board structure, and is basically the same as the PLC board.
FIG. 17 shows steps of processing by the above PLC and "PLC+personal computer". Although FIG. 17 shows the steps of processing by the board PLC shown in FIG. 16, steps of processing by the "PLC+personal computer" are performed similarly to those shown in FIG. 17.
In FIG. 17, ladder interpreter 21 of PLC board 20 first fetches and decodes a ladder program stored in user memory UM of memory 22 in PLC board 20 for performing "instruction execution" (step S101). Results of this "instruction execution" are written into I/O memory IOM, and thereby the results of the "instruction execution" are reflected on I/O memory IOM of memory 22 of PLC board 20. When one "instr
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Fukutome Goro
Ichimura Katsuhiko
Nakata Takeshi
Lee Thomas C.
Omron Corporation
Wang Albert
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