Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1996-07-09
2001-04-17
Beausoleil, Robert (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S120000, C711S002000
Reexamination Certificate
active
06219740
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an information processing device for processing information which is made up of a plurality of processors each having a register file formed on a single semiconductor chip.
2. Description of the Prior Art
Conventionally, in an information processing device of
FIG. 1
including a plurality of processors
10
(or a multi-processor information processing device) formed on a single semiconductor chip, a cache memory
11
is incorporated for each processor
10
and each cache memory
11
is electrically connected to a main memory
13
through a common bus
12
. In the prior art, there is a problem that the conventional information processing device has a poor execution efficiency or poor performance because data is transferred between the processors
10
through the main memory
13
, so that latency of a memory access operation becomes low.
In order to avoid this drawback described above and so that the processors
10
perform efficiently, data transfer operation must be performed between the cache memories
11
, not through the main memory
13
, as much as possible. In other words, the number of accesses to the main memory
13
must be reduced in the conventional information processing device. But, this causes some limitations on programs to be executed in the conventional information processing device.
Furthermore, the cache coherency problem between the cache memories
11
and the main memory
13
becomes so complicated that it must be required to form a complicated configuration of the conventional information processing device.
As described above, in the conventional information processing device having a plurality of processors, there is the drawback that the instruction execution efficiency becomes low because the data transfer operation between the processors
10
is performed through the main memory whose operation speed is low and a large amount of data transfer time between the processors
10
is required.
Moreover, because each processor has the cache memory and it must be required to store the same data into the main memory and the cache memories in the conventional information processing device as shown in
FIG. 1
, designers must design complicated hardware configurations.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional information processing device, to provide an information processing device having a plurality of processors formed on a single semiconductor chip that is capable of performing a high speed data transfer operation between the processors and of increasing an instruction execution efficiency, so that designers may easily design the information processing device.
In accordance with one aspect of the present invention, an information processing device has a plurality of processors each including a register file having a plurality of registers and exclusive data transfer buses through which specified registers in different processors in the plurality of processors are directly connected. Thus, in the information processing device of the present invention, a data read operation and a data write operation between the specified registers in the different processors are performed through the exclusive data transfer buses.
In accordance with a further aspect of the present invention, the specified registers have at least one general purpose register and at least one virtual register. The virtual register selectively receives data transferred through the exclusive buses from the other processor that is different from the processor having this virtual register, or the virtual register selectively transfers data through the exclusive data transfer buses to the processor that is different from the processor having this virtual register.
In accordance with another aspect of the present invention, the specified registers have at least one virtual register and at least one extension register that is incorporated for each virtual register. The virtual register selectively receives data transferred through the exclusive data transfer buses from the other processor that is different from the processor having this virtual register, or the virtual register selectively transfers data through the exclusive buses to the processor that is different from the processor having this virtual register. Data may be read from the extension register or written into the extension register in the processor having this extension register independently from the other processors.
In the information processing device of this embodiment, the virtual register is made up of a MOS FET whose source or drain terminal is connected to the exclusive bus and whose gate terminal is connected to a control bus (or a word line) for accessing the virtual register. The source or drain terminal is connected to a readout port through which data in the virtual register is read.
In the information processing device of this embodiment, each of the general purpose registers and the extension registers is made up of a memory circuit consisting of a flip-flop circuit to store data and a MOS FET. The MOS FET is placed between the memory circuit (namely, the flip-flop circuit) and a readout port or a write-in port. Data stored in the memory circuit is read to outside through the readout port or data from outside is written into the memory circuit through the write-in port. The source or drain terminal of the MOS FET is connected to the readout port or the write-in port and the gate terminal of the MOS FET is connected to a control line (or a word line) for accessing the general purpose register or the extension register.
In accordance with another aspect of the present invention, an information processing device comprises a plurality of processors each having a register file including at least a virtual register and an extension register. The plurality of processors are connected circularly through the exclusive data transfer buses and the virtual register in each processor is connected to the extension register in a previously stage through an exclusive data transfer bus.
The information processing device of this embodiment further comprises a main memory, and each of the plurality of processors accesses the main memory with a different fixed address.
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patent: 4939636 (1990-07-01), Nakagawa et al.
patent: 5361340 (1994-11-01), Kelly et al.
patent: 5440689 (1995-08-01), Reilly et al.
patent: 5507026 (1996-04-01), Fukushima et al.
patent: 5509137 (1996-04-01), Itomitsu et al.
patent: 5548592 (1996-08-01), Komarek et al.
patent: 5553252 (1996-09-01), Takayanagi et al.
patent: 5664161 (1997-09-01), Fukushima et al.
Beausoleil Robert
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Vo Tim
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