Information processing apparatus with reduced power consumption

Details Information processing apparatus with reduced power consumption Information processing apparatus with reduced power consumption

1998-06-08

2001-02-27

An, Meng-Ai T. (Department: 2783)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S320000, C713S321000, C713S323000, C713S324000

Reexamination Certificate

active

06195753

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an information processing apparatus and, more particularly, to an information processing apparatus having a power control function.
2. Description of the Prior Art
An information processing apparatus such as a microprocessor having a power saving control function has been known (Japanese Unexamined Patent Publication Nos. 63-26716 and 3-10306).
FIG. 1
is a circuit diagram showing an overall arrangement of this conventional information processing apparatus. In the conventional information processing apparatus, an instruction designated by a program counter
1
is loaded from an instruction memory
2
into an instruction register
3
in synchronism with a clock CL
1
. An instruction decoder
4
decodes the instruction loaded into the instruction register
3
. As a result, a function block selection signal associated with the execution of the instruction is activated in synchronism with a clock CL
2
.
The logic of each active output signal from the instruction decoder
4
is inverted by a corresponding one of inverters
5
a
to
5
n
. Each inverted signal is then input to one input terminal of a corresponding one of two-input AND circuits
6
a
to
6
n
. Meanwhile, a clock CL
3
, for determining the operation timing of each function block, is commonly input to the other input terminal of each of the two-input AND circuits
6
a
to
6
n through a buffer
10
.
The output signals from the two-input AND circuits
6
a
to
6
n
are respectively supplied to function blocks
8
a
to
8
n
through buffers
7
a
to
7
n
arranged in correspondence with the two-input AND circuits
6
a
to
6
n
. With this connection, the clock CL
3
is supplied to only the function block, of the function blocks
8
a
to
8
n
, which is used for each instruction, but the remaining function blocks that are not used do not operate. This can reduce the overall power consumption.
Although not described in the above reference, each of the function blocks
8
a
to
8
n
does not operate singly, and the respective function blocks operate in association with each other in the actual information processing apparatus. For this reason, the apparatus uses a inter-function-block control signal
9
. The operation of the inter-function-block control signal
9
will be described for a case where the contents of the memory are loaded into the instruction register. In this case, a register circuit and a memory access circuit serve as function blocks.
When an instruction is decoded, a clock is supplied to these two function blocks to start the operation. The memory access circuit as one function block outputs a memory read request to the outside of the information processing apparatus, waits for a response from the outside, and receives data. The memory access circuit then writes the data in the register by using the register circuit as the other function block. In this case, memory access depends on the external state (for example, in the case of a dynamic random access memory (DRAM), no response is received during memory refresh operation).
The memory access circuit must therefore keep operating (monitoring) to prepare for the reception of data at any moment. The memory access circuit must also notify the register circuit that the data has been received (or will be received). The inter-function-block control signal
9
includes a control signal for the notification of such a state between these function blocks.
An information processing apparatus using a semiconductor device takes two types of circuit arrangements, namely a static circuit and a dynamic circuit. The static circuit establishes a stable state by using transistors, and stably operates independently of the clocks. The dynamic circuit uses interconnection capacitances. More specifically, this dynamic circuit uses the charge stored in the capacitances to suppress the number of transistors to be used, thereby attaining a high integration degree. Since the dynamic circuit uses the charge in the interconnection capacitances, the circuit stops operating a given period of time after the charge is discharged. For this reason, the dynamic circuit has a lower operating frequency limit.
In the above conventional information processing apparatus, clock control on the respective function blocks is determined by only decoding of instructions, but does not depend on the internal state of respective function blocks. For this reason, unnecessary function blocks may operate to consume excess power. In the above case of memory read access, the register function block in the memory access completion wait state is an unnecessary block.
In the information processing apparatus having the semiconductor circuit using the dynamic circuit, because of the lower operating frequency limit described above, when the clock is completely stopped, the internal state of a function block changes. As a result, the block may not operate properly.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above problems in the prior art, and has as its object to provide an information processing apparatus which can attain a reduction in power consumption as compared with the prior art by stopping unnecessary function blocks from consuming power.
In order to achieve the above object, according to the first aspect of the present invention, there is provided an information processing apparatus comprising an instruction memory for storing an instruction, an instruction register in which the instruction in the instruction memory is loaded, a plurality of function blocks for performing a basic operation required for execution of the instruction, an instruction/state decoder for decoding the instruction read out from the instruction register, and also decoding a control signal for notification of a state between the function blocks, and a clock supply/stop circuit for supplying a clock to only a function block, of the plurality of function blocks, which is required for execution of the decoded instruction and needs to operate, on the basis of an output signal from the instruction/state decoder.
In the first aspect, since a control signal for the notification of a state between function blocks is fed back to the instruction/state decoder, a clock for controlling the operation of each function block is supplied to each function block to cause it to operate, on the basis of the result obtained by decoding an instruction and an inter-function-block control signal, only when each function block must truly operate.
According to the second aspect of the present invention, there is provided an information processing apparatus comprising an instruction memory for storing an instruction, an instruction register in which the instruction in the instruction memory is loaded, a plurality of function blocks for performing a basic operation required for execution of the instruction, an instruction/state decoder for decoding the instruction read out from the instruction register, and also decoding a control signal for notification of a state between the function blocks, a plurality of clock generators for generating first and second clocks having different frequencies, and a clock supply/stop circuit for supplying the first clock having a high frequency to only a function block, of the plurality of function blocks, which is required for execution of the decoded instruction and needs to operate, and supplying the second clock having a low frequency to a function block which need not operate, on the basis of an output signal from the instruction/state decoder.
In the second aspect, when each function block must truly operate, the first clock is input to cause it to operate. When each function block need not operate, the second clock is input to it. By setting the second clock to the lower operating frequency limit of the circuit, dynamic circuits can be used to form each function block.
According to the present invention, a clock for controlling the operation of each function block is supplied to the function blo

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