Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
2007-01-02
2007-01-02
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S105000, C711S202000
Reexamination Certificate
active
10702482
ABSTRACT:
In an information processing apparatus involving a cache accessed by INDEX and TAG addresses, accesses to the main memory include many accesses attributable to the local character of referencing and write-back accesses attributable to the replacement of cache contents. Accordingly, high speed accessing requires efficient assignment of the two kinds of accesses to banks of the DRAM. In assigning request addresses from the CPU to different banks of the DRAM, bank addresses of the DRAM and generated by operation of the INDEX field and the TAG field so that local accesses whose INDEX varies and accesses at the time of writing back of which INDEX remains the same but TAG differs can be assigned to different banks. High speed accessing is made possible because accesses to the main memory can be assigned to separate banks. Furthermore, as reading and writing at the time of writing back can be assigned to a separate bank, pseudo dual-port accessing is made possible with only one port, resulting in higher speed write-back accessing.
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Kanno Yusuke
Mizuno Hiroyuki
Watanabe Takao
Hitachi , Ltd.
Mattingly ,Stanger ,Malur & Brundidge, P.C.
Thai Tuan V.
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