Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
1998-08-27
2002-02-05
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S118000
Reexamination Certificate
active
06345350
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an information processing apparatus applicable for use as a printer control unit using ROM, RAM and further a high-speed RAM incorporated in CPU.
2. Related Art
In an information processing apparatus forming an image processing unit of a page printer, as shown in
FIG. 9
, a program to be executed in a CPU
11
is stored in a ROM
12
. When power is supplied to the information processing apparatus like this, the CPU
11
is first loaded with an initial setting program (IPL)
21
stored in the ROM
12
as shown in FIG.
10
and at Step ST
1
, hardware such as various interfaces (not shown) is initially set. Then jumping to the head address of a print processing program
22
of the ROM
12
is made at Step ST
2
and print processing is started according to the statement of the print processing program
22
at Step ST
3
.
FIG. 11
shows an example of the memory space to which the ROM
12
has been allocated. The program space of a RAM
14
for use as a system memory (main memory) is allocated from an address [00000000] and the address space of the a ROM
13
for storing a font bit map data is allocated from a high-order address [1F800000] and further the address space for storing a program is allocated from an address [1FC00000]. When the CPU
11
obtains access to each of the memory addresses, a decoder
16
provided for a memory controller
15
decodes the address and supplies to each chip a chip select signal for selecting the ROM
12
, the ROM
13
or the RAM
14
allocated to the address involved, so that data transfer is made between the CPU
11
and each chip.
All the address values shown in the present specification or any other one are only exceptional and cannot restrictively be interpreted.
The head address [1FC00000] allocated to the ROM
12
is made to the head address of the IPL
21
and when power is supplied, the CPU
11
interprets the command described at this address and operates to start. When the initial setting of the hardware is terminated, jumping to the head address [1FD00000] of the print processing program
22
is made and thereafter the CPU
11
operates according to the print processing program (executing program)
22
.
Since the page printing printer deals with a large quantity of information, it tends to take a great deal of time necessary for interpreting the input data supplied from the personal computer on the host side and the like and translating the data into intermediate print codes and output data to be supplied to a printing mechanism. Consequently, it becomes important to improve the processing speed of the whole processing apparatus. In order to improve the processing speed, increasing the processing capacity of the CPU and improving the data transfer speed between the CPU and memories are effective. However, the ordinary ROM is accessible only at low speed and the processing speed of the whole processing apparatus is saturated with the data transfer speed with the ROM. Although CPUs offering high processing speed become available at relatively low prices in recent years, the processing speed of the whole processing apparatus is impossible to double even though the operating frequency of the CPU is rendered, for example, twice because the data transfer is needed with respect to the ROM. Consequently, though the use of a ROM offering transfer speed as high as possible is desired to build a system, such a high-speed, large-capacity ROM is absent at present and besides extremely costly. Since a ROM having a large storage capacity is required to store a program necessary for the processing of the page printer, it is actually very difficult to form a system by the use of a high-speed ROM.
The RAM can be operated at high speed in comparison with the ROM and what offers a large capacity is obtainable at relatively low prices. It may therefore be taken into consideration to copy the print processing program
22
stored into the ROM
12
in the RAM
14
and to execute the program at the time power is supplied. However, copying the print processing program
22
into the RAM
14
causes part of the RAM space used as the system memory area of the memory map
9
to be monopolized by the print processing program
22
and results in curtailing a memory capacity usable for image processing. For this reason, the data processing time necessary for color printing and high resolution printing may be prolonged.
Although the print processing program on the ROM may be considered separately usable from the print processing program copied into the RAM depending on the use condition of the RAM, different programs become necessary because there is a difference in the address on the memory space between the ROM and RAM. Consequently, two programs have to be stored in the ROM, namely, a program to be executed on the ROM and what is to be copied into the RAM and executed and this makes a large capacity ROM. Moreover, there is still a problem arising from an increase in the program development cost because two different programs need to be developed and maintained.
It is also being examined recently to employ a CPU incorporating a DRAM of about 2-3 MB together with a CPU core as a printer control system. Although the storage capacity of the DRAM incorporated in the CPU is not limited to the aforementioned, a DRAM having an extremely large storage capacity is difficult to contain in the CPU in view of the size of a CPU chip and production cost now. Notwithstanding, the processing speed can be maximized on condition that the program is copied into the DRAM incorporated in this CPU and executed because a chip-to-chip interface or the access speed of a bus for use in connecting chips is not restricted. As a result, a program can be executed at the highest speed if the program is copied into the high-speed RAM but there still remains the aforesaid address problem. Moreover, though the processing speed in a case where a working area is set in the high-speed RAM incorporated in the CPU may become higher than a case where the program is copied and executed the setting of addresses becomes complicated further and besides the processing time is prolonged. Furthermore, memories offering higher processing speed are expensive because of various reasons. Consequently, securing a sufficient memory capacity for the storage and working areas of such a program with respect to whole processing results in not only over-specification but also an increase in costs.
SUMMARY OF THE INVENTION
The present invention was made in view of the foregoing difficulties accompanying the conventional information processing apparatus. Therefore, an object of the present invention is to provide an information processing apparatus having a plurality of memories different in kinds such as ROMs and RAMs capable of executing a common executing program, capable of executing a problem on a suitable memory or setting a working area thereon.
Another object of the present invention is to provide an information processing apparatus and a method of controlling an information processing apparatus capable of improving the processing speed of the whole apparatus by optimizing the allocation of memory spaces to a RAM externally connected to a CPU or a high-speed RAM incorporated in the CPU.
It is still another object of the present invention to provide a printer offering a high printing speed using an information processing apparatus capable of performing bulk data processing such as image information by flexibly setting memory areas.
It is also a further object of the present invention to provide a method of controlling an information processing apparatus capable of executing programs by switching the programs on a plurality of memories, and a record medium stored with a program which makes the processing performable.
In an information processing apparatus having a plurality of memories different in speed according to the present invention, part of or the whole of the address of the s
Maruyama Mitio
Utsumi Kazuyoshi
Chace Christian P.
Kim Matthew
Seiko Epson Corporation
Sughrue & Mion, PLLC
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