Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-02-11
2004-09-14
Whitmore, Stacy A. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06792583
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to design of a semiconductor integrated circuit.
Conventionally, a semiconductor integrated circuit is designed by a designer through an interactive operation using a terminal device.
JP-A-10-79436 describes such a technology of the prior art in which an allocation state of blocks is displayed on a display according to allocation information of blocks stored in a storage, and blocks indicated from an input device are interactively allocated and moved.
JP-A-9-330350 describes an apparatus in which when a circuit including a plurality of elements are arranged in a predetermined mounting area to draw a layout thereof, the elements are allocated to reflect a relative positional relationship among the elements on the circuit diagram. Namely, during the execution of an allocation search of elements in an algorithm or in a heuristic method, a user interactively intervenes in the search so that the searching ability of the algorithm or heuristics and the empirical knowledge or judging ability of the user interact with each other. Thereby, it is possible to obtain the allocation results with high quality in a short period of time.
With advance of technology, the number of gates to be integrated in one chip is increasing. Therefore, it is almost difficult to design again all logical circuits to be integrated because of a large amount of human power required for the design and verification of the integrated circuit. In order to reduce the number of designing steps in the designing of a large scale integrated circuit (LSI), there has been increasingly employed an idea of re-use of design. That is, “the new designing steps are minimized by configuring an LSI with a plurality of blocks for which the existing blocks already designed are used, if possible”. A block for which an existing block is used is called as “a virtual component (VC)”, “an intellectual property (IP)”, or “a core”.
By reusing the existing blocks, some of blocks constituting a certain LSI are added to the blocks of an LSI, so that it is possible to easily construct the LSI capable of achieving a required function.
However, any LSI having a predetermined function cannot be necessarily manufactured by such a simple addition and removal of the existing blocks.
The allocation of blocks constituting an LSI is determined by a floorplan which is the allocation information of blocks. The designer defines the circuit description to determine the functions of blocks constituting the LSI. Namely, the characteristics of blocks are determined according to the circuit description. Usually, the designer defines the floorplan together with the block circuit description.
Consequently, when the floorplan is modified through the removal and addition of the blocks without paying attention to the circuit description and by ignoring the characteristics of blocks, a resultant LSI may not satisfactorily function in some cases.
In JP-A-10-79436, a floorplan is interactively edited, so that the designer must generate the floorplan in order that the LSI can satisfactorily function.
JP-A-9-330350 describes a floorplan at a level of elements of an LSI, but consideration has not been given to a floorplan of blocks. Moreover, in order to generate a floorplan, it is required to intervene in the interactive operation of the user so that the empirical knowledge or judging ability of the operator of the tool and the processing of the tool must interact with each other.
That is, when the floorplan is modified in the prior art, it is necessary for the user to have the knowledge at the level of the designer.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an information processing apparatus for modifying a floorplan in which an LSI is not deteriorated in performance even if a user has not the knowledge of a designer, thereby solving the problem above.
The object will be achieved according to the present invention as follows. A designer of a semiconductor integrated circuit beforehand generates circuit information for indicating functions of blocks constituting the semiconductor integrated circuit, and a floorplan regarding allocation of the blocks. The circuit information and the floorplan are stored with being associated with evaluation indices for evaluating modification of the floorplan.
Thereby, when a user modifies the floorplan, the user can evaluate the modified floorplan according to the evaluation indices. Namely, the user can modify the floorplan without deteriorating the performance of the LSI even if the user has no know-how of the designer.
The objects and features of the present invention will become more apparent from the consideration of the following detailed description taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 4918614 (1990-04-01), Modarres et al.
patent: 5910899 (1999-06-01), Barrientos
patent: 6002857 (1999-12-01), Ramachandran
patent: 6170080 (2001-01-01), Ginetti et al.
patent: 6243851 (2001-06-01), Hwang et al.
patent: 0294188 (1988-12-01), None
patent: A-10-79436 (1989-03-01), None
patent: A-9-330350 (1997-12-01), None
Hirotsu Teppei
Hotta Takashi
Shimamura Kotaro
Takahashi Yoshitaka
Tomobe Katsuichi
Antonelli Terry Stout & Kraus LLP
Renesas Technology Corp
Whitmore Stacy A.
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