Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2001-12-28
2004-01-20
Cho, James H (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S026000, C333S124000
Reexamination Certificate
active
06680623
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to information processing apparatuses and, more particularly, to an information processing apparatus having a plurality of modules connected to a high-speed bus.
2. Description of the Related Art
In recent years, in the computer field, data transmission rate has been increased with improvements in the processing speed. For example, on a motherboard, data transmission between a memory and a system controller is performed at a data transmission rate of 266 MHz.
The improvements in the data transmission rate causes a problem relates to an influence of impedance mismatching of buses provided on a motherboard. In order to increase the data transmission rate of a motherboard, it is necessary to match the impedance on a bus.
In a conventional motherboard, modules are arranged as close as possible to each other or a series resistor is provided in the modules so as to correspond to an increase in the data transmission rate. The conventional motherboard can mount a maximum of four memory modules such as DDR SDRAM (Double Data Rate Synchronous DRAM) modules having a data transmission rate of 266 MHz.
FIG. 1
shows a diagram of an equivalent circuit of a part of a conventional motherboard. The equivalent circuit of the part of the motherboard
1
includes a controller
11
, a wiring
12
, memory modules
13
and a terminating resistance
14
. The controller
11
is connected to the memory module
13
via the wiring
12
so as to control the memory module
13
. The wiring
12
is provided on the motherboard and has a characteristic impedance being set to Z
0
. An internal wiring
15
of the memory module
13
has a characteristic impedance being set to Zm.
An impedance Zcont of a point A when seen from the controller
11
side and an impedance Zmem of the point A when seen from the memory module
13
side are represented by the following equations.
Zcont=
1/((1
/Zm
)+(1
/Z
0
)) (1)
Zmem=
1/((1/Z
0
)+(1
/Z
0
)) (2)
It is desirous to set the impedances Zcont and Zmem to be as follows.
Zcont=Z
0
(3)
Zmem=Zm (4)
However, such a solution does not exist in the above-mentioned equations (1) and (2).
Here, if Z
0
=50 &OHgr; and Zm=75 &OHgr;, it is set to Zcont=30 &OHgr; and Zmem=25 &OHgr; from the equations (1) and (2).
As indicated in the above-mentioned equations (3) and (4), since an ideal impedance of Zcont is 50 &OHgr; and an ideal impedance of Zmem is 75 &OHgr;, there is a large mismatch between the ideal impedances and the actual impedances.
According to the conventional connecting method of a memory module, the impedance Zmem at a branch point becomes 25 &OHgr; when the memory module
13
is seen from the wiring
12
due to mismatching of characteristic impedances. This impedance is a value far smaller than the ideal impedance Zmem=75 &OHgr;.
For this reason, there is a problem in that a signal distortion occurs in a transmission signal due to a reflective wave.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide an improved and useful image processing apparatus in which the above-mentioned problems are eliminated.
A more specific object of the present invention is to provide an information processing apparatus which can reduce a transmission distortion of a signal transmitted between a module and a controller.
In order to achieve the above-mentioned objects, there is provided according to the present invention an information processing apparatus comprising: a circuit board; a plurality of modules mounted on the circuit board; a controller mounted on the circuit board so as to control the modules; a bus line connecting the controller to the modules, the bus line including a main line and a plurality of branch lines each of which is branched from the main line and is connected to a respective one of the modules; and impedance matching elements provided to the main line of the bus line so as to match a characteristic impedance between the controller and each of the modules, each of the impedance matching elements being located behind a branch point of one of the branch lines connected to the respective one of the modules with respect to the controller.
In one embodiment of the present invention, each of the impedance matching elements may be a chip inductor or an inductance element.
Additionally, the modules may be mounted on the circuit board via a predetermined number of connectors previously mounted on the circuit board, and a dummy module having an impedance equal to an impedance of each module may be attached to one of the connectors to which the module is not attached.
Additionally, there is provided according to another aspect of the present invention a circuit bard comprising: a plurality of modules mounted on the circuit board; a controller mounted on the circuit board so as to control the modules; a bus line connecting the controller to the modules, the bus line including a main line and a plurality of branch lines each of which is branched from the main line and is connected to a respective one of the modules; and impedance matching elements provided to the main line of the bus line so as to match a characteristic impedance between the controller and each of the modules, each of the impedance matching elements being located behind a branch point of one of the branch lines connected to the respective one of the modules with respect to the controller.
Further, there is provided according to another aspect of the present invention a connecting method of a plurality of modules to a controller mounted on a circuit board, comprising the steps of: preparing a bus line formed on the circuit board so as to connect the controller to the modules, the bus line including a main line and a plurality of branch lines each of which is branched from the main line and is connected to a respective one of the modules; and applying impedance matching of a characteristic impedance between the controller and each of the modules, the impedance matching being performed at a location behind a branch point of one of the branch lines connected to the respective one of the modules with respect to the controller.
According to the above-mentioned invention, impedance matching is achieved between the controller and each of the modules at a location behind a branch point of each branch line with respect to the controller. Thus, a distortion of transmission waveform of a transmission signal can be reduced, thereby increasing a signal transmission rate and increasing a number of modules mountable to the circuit board.
Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.
REFERENCES:
patent: 5955889 (1999-09-01), Taguchi et al.
patent: 6067594 (2000-05-01), Perino et al.
patent: 6438012 (2002-08-01), Osaka et al.
patent: 52-87934 (1977-07-01), None
patent: 2000-267775 (2000-09-01), None
Hirai Tendo
Serizawa Atsushi
Arent Fox Kintner Plotkin & Kahn
Cho James H
Fujitsu Limited
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