Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2000-05-01
2001-12-11
Ellis, Kevin L. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S154000, C713S600000
Reexamination Certificate
active
06330651
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to an information processing apparatus such as a personal computer, a work station or the like, and more particularly to a method of controlling a memory provided in such an apparatus.
2. Description of the Related Art
In recent years, an information processing apparatus such as a personal computer, a work station or the like has kept on being miniaturized as well as being promoted with respect to the high performance. The throughput of a microprocessor which is the main unit of such an information processing apparatus has been rapidly enhanced by being supported by the progress of the semiconductor process technology. Thus, the product has appeared which exhibits the high performance at a high operation frequency while keeping the power consumption low. Along with such rapid enhancement of the capability of the microprocessor, the memory is required which can cope with the enhanced throughput of the microprocessor. Then, as for the new memory device which compensates for a difference between the capability of the microprocessor and that of the memory device, a synchronous dynamic random access memory device (hereinafter, referred to as “a synchronous DRAM device” for short, when applicable) has appeared in the market.
The synchronous DRAM device serves to carry out the operation of reading out the data every one clock period for the request of reading out the data synchronously with the given driving clock signal, and has the feature in which it can cope with the high operation frequency of the microprocessor. At the present time, the synchronous DRAM device which can cope with the driving clock frequency of 100 MHz (one clock signal corresponds to 10 ns) has been manufactured. As for such a memory control method, there is known the technology which is disclosed in JP-B-60-3699 for example.
In the case where the synchronous DRAM device as described above is applied to a memory system of the information processing apparatus, for the performance of an input-output buffer of an LSI for controlling a memory, the temperature and the power source voltage, the dispersion in characteristics of the synchronous DRAM device against the change in the operation environment needs to be taken into consideration. The dispersion in the characteristics of the synchronous DRAM device due to the change in the operation environment is an obstacle to bringing out the high operation performance of the synchronous DRAM device and as a result the driving clock frequency of the current practical memory system is limited to about 33 MHz (one clock signal corresponds to 30 ns). Therefore, it can be said that under the present circumstances, it is impossible to make the best use of the high speed reading performance of the synchronous DRAM device as much as possible.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an information processing apparatus which is capable of reading out the data from the synchronous DRAM device on the basis of the driving clock signal of the high frequency irrespective of the change in the operation environment.
According to the present invention, an information processing apparatus is constructed by including a memory unit for storing the data and a control unit for controlling the operation of reading/writing the data from/to the memory unit. According to the preferred aspect, the memory unit outputs the data synchronously with an inputted clock signal. A first wiring through which the clock signal is delivered from the control unit to the memory unit, a second wiring through which the data is delivered from the memory unit to the memory control unit, and a third wiring which branches from the first wiring in order to pull back the clock signal to the memory control unit are respectively distributed between the memory unit and the memory control unit. The memory control unit includes a storage unit for storing the data, which has been read out from the memory unit, at the timing which is determined on the basis of the clock signal which has been pulled back through the third wiring.
More preferably, the branch of the third wiring from the first wiring is provided in the vicinity of the memory unit, and the clock signal just before delivered to the storage unit is pulled back to the control unit, and the control unit fetches the data in the storage unit at the timing of that clock signal.
Each of the data which has been outputted from the storage unit synchronously with the clock signal to be delivered to the control unit, and the clock signal which has been pulled back to the control unit through the third wiring contains both a delay due to the wiring and a delay due to an internal circuit of the control unit. While those delays are changed by the change in the environment, those delays are contained in the data delivered to the control unit as well as in the clock signal thus pulled back, whereby the delay of the data and the delay of the clock signal pulled back are changed with the same tendency by the change in the environment. Therefore, it is possible to reduce the variable difference between the delay of the data and the delay of the clock signal. As a result, the data which has been outputted synchronously with the clock signal can be always written to the storage unit at the same timing irrespective of the change in the environment, and hence it is possible to increase the clock frequency. As a result, it is possible to construct the information processing apparatus which is capable of fetching the data from the storage unit at the high speed.
REFERENCES:
patent: 5462756 (1995-10-01), Saito et al.
patent: 5479647 (1995-12-01), Harness et al.
patent: 5577236 (1996-11-01), Johnson et al.
patent: 5623638 (1997-04-01), Andrade
patent: 060-3699 (1980-11-01), None
Kamimaki Hideki
Kawaguchi Hitoshi
Kimura Koichi
Kobayashi Kazushi
Tamura Takayuki
Antonelli Terry Stout & Kraus LLP
Ellis Kevin L.
Hitachi , Ltd.
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