Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
1999-04-09
2002-04-23
Elmore, Reba I. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S001000, C711S101000, C711S131000
Reexamination Certificate
active
06378050
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to information processing apparatuses and storage mediums, and more particularly to an information processing apparatus which is designed to carry out a cache control or a DMA control by judging whether an input request is a cache control request or a DMA control request, and to a computer-readable storage medium which stores in a hardware description language circuit information which is used to design such an information processing apparatus by a computer.
2. Description of the Related Art
FIG. 1
is a system block diagram showing an example of a conventional information processing apparatus. The information processing apparatus includes a Reduced Instruction Set Computer (RISC) processor
201
for data processing, a cache memory
202
, a signal processing digital signal processor (DSP)
203
for signal processing, a memory
204
with direct memory access (DMA), a memory bus
205
, and a main storage part
206
which are coupled as shown in FIG.
1
. For example, the RISC processor
201
is provided to carry out the data processing such as a communication protocol, and the DSP
203
is provided to carry out a high-speed signal processing. Recently, there is active development in media processing systems which carry out a high-speed signal processing with respect to image, audio, computer graphics and the like. An information processing apparatus having the RISC processor
201
and the DSP
203
provided on a single chip has also been proposed.
However, according to the information processing apparatus described above, the RISC processor
201
and the DSP
203
are provided independently of each other. For this reason, there was a problem in that the programming is difficult since independent instruction codes must be generated with respect to the RISC processor
201
and the DSP
203
when the user programs the information processing apparatus.
In addition, in order to make a high-speed access to a low-speed main storage part having a large storage capacity, a technique which is generally employed provides a high-speed memory having a small storage capacity between a processor and the main storage part, so as to form a cache memory system or a memory system with DMA. However, when the RISC processor
201
and the DSP
203
are provided as described above, it becomes necessary to form the cache memory system or the memory system with DMA independently with respect to the RISC processor
201
and the DSP
203
. More particularly, it is necessary to provide a cache memory system which includes the cache memory
202
with respect to the RISC processor
201
, and to provide a memory system with DMA which includes the memory
204
with DMA with respect to the DSP
203
, independently of the cache memory system. For this reason, there was another problem in that the construction of the memory system becomes complex, and the cost of the entire information processing apparatus becomes high.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a novel and useful information processing apparatus and storage medium, in which the problems described above are eliminated.
Another and more specific object of the present invention to provide an information processing apparatus which can efficiently process a cache control request and a DMA control request using a relatively simple and inexpensive construction, and a computer-readable storage medium which stores circuit information which is written in a hardware description language and is used to design such an information processing apparatus.
Still another object of the present invention is to provide an information processing apparatus comprising judging means for decoding an address of an input request and outputting a judgement signal which indicates whether the input request is a cache control request or a DMA control request, and control means for carrying out a cache control when the judgement signal from the judging means indicates the cache control request, and carrying out a DMA control when the judgement signal indicates the DMA control request. According to the information processing apparatus of the present invention, it is possible to efficiently process a cache control request and a DMA control request using a relatively simple and inexpensive construction.
The information processing apparatus may further comprise a single memory part including a first region which forms a cache memory part used for the cache control, and a second region which forms a data memory part used for the DMA control. The control means may include means for variably setting a ratio of the first and second regions based on a parameter. The memory part may have a multi-port structure. In addition, each part of the information processing apparatus may be provided on a single chip.
A further object of the present invention is to provide a computer-readable storage medium which stores circuit information in a hardware description language, comprising a first data region storing circuit information related to a judging means for decoding an address of an input request and outputting a judgement signal which indicates whether the input request is a cache control request or a DMA control request, and a second data region storing circuit information related to a control means for carrying out a cache control when the judgement signal from the judging means indicates the cache control request, and carrying out a DMA control when the judgement signal indicates the DMA control request. According to the computer-readable storage medium of the present invention, it is possible to make a computer efficiently process a cache control request and a DMA control request using a relatively simple and inexpensive construction.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.
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patent: 4580240 (1986-04-01), Watanabe
patent: 4928225 (1990-05-01), McCarthy et al.
patent: 5029070 (1991-07-01), McCarthy et al.
patent: 5586293 (1996-12-01), Baron et al.
patent: 6023757 (2000-02-01), Nishimoto et al.
patent: 0 529 217 (1993-03-01), None
patent: 2 284 911 (1995-06-01), None
patent: 63-98749 (1988-04-01), None
patent: 4-88537 (1992-03-01), None
Nomura Yuji
Tsuruta Toru
Elmore Reba I.
Fujitsu Limited
Staas & Halsey , LLP
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