Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2000-08-11
2003-08-12
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S006000, C709S213000
Reexamination Certificate
active
06606697
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an information processing apparatus that adopts a virtual storage system. More particularly, the invention relates to a memory control method that constructs a virtual computer system, using a translation table indicating a correspondence between a guest virtual address and a host real address as an address translation table.
2. Description of the Related Art
A virtual storage system generally controls a correspondence between a virtual memory space and a real memory space, using the unit of block called “page.”
FIG. 3
shows a conception of translating a virtual address to a real address. A virtual address
310
comprises a virtual page number
311
and a page offset
312
. A page table
331
is an address translation table allocated to a real memory space (main storage)
320
, and the page table
331
stores real addresses (real pages) of individual virtual pages. Supposing the virtual page number is represented as “n,” the real address of each virtual page is stored in line
332
in the n-th location. A page table base register (PTBR)
330
indicates the real address (page table address pointer) of the page table
331
, which is currently used by a processor (real computer), on the real memory space
320
. By rewriting the PTBR
330
, two or more page tables, i.e., two or more virtual spaces can be switched/used.
Translation from a virtual address to a real address is outlined as follows:
(1) Calculate the page table
331
on the real memory space
320
(main storage) by referring to the PTBR
330
.
(2) Calculate a real page stored in the line
332
on the page table
331
, depending on the virtual page number
311
in the virtual address
310
.
(3) Add the page offset
312
of the virtual address
310
to the low-order bit of the real page, assuming the added real page as a real address, and access the real memory space
320
, depending on the real address.
In this manner, the virtual storage system refers to the page table when calculating the real address, so the real memory needs to be accessed twice each time the virtual memory is accessed. To prevent this overhead, generally a processor contains a high-speed address translation buffer memory called “Translation Look aside Buffer (TLB)”, and saves in the TLB a correspondence between a virtual page number and a real address (real page), which have been calculated by referring to the page table. If the entry of a virtual page number has been registered in the TLB, the processor searches the TLB and immediately calculates a real address from the entry, when translating the address. Only if the entry of the virtual page number has been unregistered in the TLB, the processor calculates the real address by referring to the page table on the main storage. Then, the processor newly registers the correspondence between the virtual page number and the real address (real page) in the TLB.
When the processor contains the TLB, a software controlling the virtual storage needs to invalidate the content of the TLB (called “TLB purge”) to avoid incorrect translation, similarly to an operating system (abbreviated “OS”), when the page table has been rewritten or when the page table base register (PTBR) has been rewritten. A TLB purge occurs in the following cases:
(1) When an instruction of purging a specific entry in the TLB (hereafter called “Entry Purge instruction”) is executed.
(2) When an instruction of writing from a program to the PTBR (hereafter called “explicit rewrite”) is executed.
(3) When a PTBR rewrite is executed with a task switch.
Then, a brief explanation for the task switch will be made. An information processing apparatus comprises a memory area, called “task state segment (abbreviated as TSS),” for each task, where the processor status is saved when switching a task. For example, when task A is switched to task B, the processor executes the following processing:
(1) Save the register value (including a PTBR value) of the processor during executing a task switch instruction, in the task A TSS.
(2) Write a value from the task B TSS to a register in the processor.
Therefore, if the task B is switched to the task A later, the processor status before the task switch, is restored, depending on the task A TSS value saved in step (1).
On the other hand, a virtual computer system virtually operates one or more OSs on one real computer. For this system, a program called “host” (generally called “VMCP”) controls the real computer, generates one or more virtual computers (VM), and operates an independent OS (called “guest”) on each virtual computer.
FIG. 4
shows the conception of the virtual computer system. This conception represents that OS
1
and OS
2
operate independently as a guest A
410
and a guest B
420
each under the control of VMCP as a host
400
, and that each OS controls applications (AP).
For allocating hardware resources of a single real computer to each virtual computer, there are two methods, i.e., a method of allocating the hardware resources by time-sharing, and a method of logically dividing the hardware resources and allocating the divided resources to each virtual computer. When the virtual computer system controls a memory, the latter method is generally adopted. In this case, the host logically divides the real memory space and allocates a divided area to each guest.
FIG. 5
shows a conception of memory control performed by the virtual computer system as described above. In this embodiment, a part
541
of a real memory space
540
in the host is allocated to the guest A, and a part
542
of the real memory space
540
in the host is allocated to the guest B. Actually, the host generates a host virtual space
521
on the real memory area
541
, and the guest A operates, assuming the host virtual space
521
as a real memory space (guest real space). Similarly, the host generates a host virtual space
542
on a real memory area
522
, and the guest B operates, assuming the host virtual space
542
as a real memory space (guest real space). In addition, the guest A generates a guest virtual space
501
, and the guest B generates a guest virtual space
502
. In this case, guest translation tables (guest page tables)
511
and
512
controlled each by the guests A and B, as well as host translation tables (host page tables)
531
and
532
controlled each by the host are used as address translation tables. The guest translation tables
511
and
512
each store the guest real address (host virtual address) of each guest virtual page, and the host translation tables
531
and
532
store the host address of each host virtual page.
When the virtual computer system performs the memory control, as shown in
FIG. 5
, address translation is performed with the following procedure, when a processor accesses a guest virtual space. In this case, the guest virtual space of the guest A is a target to be accessed. The guest virtual space of the guest B is also accessed with the same procedure. However, an explanation for the PTBR is omitted for simplification.
(1) Translate a guest virtual address (guest virtual page) of the guest virtual space
501
to a guest real address (guest real page), i.e., a host virtual address (host virtual page) by referring to the guest translation table
511
. This is called “guest address translation.”
(2) Translate the guest real address, i.e., the host virtual address to the host real address (host real page) by referring to the host translation table
531
. This is called “host address translation.” This host real address indicates a physical area
541
allocated to the guest A on the real memory space
540
.
When the processor comprises a TLB, the processor saves a correspondence between a guest virtual address (guest virtual page) and a host real address (host real page) in the TLB, which has been calculated by referring to a guest translation table and a host translation table. First, the processor refers to the TLB when accessing a guest virtual space. If the entry of a guest virtual page number
Kawahara Kuniaki
Seki Yukihiro
Shimojo Takashi
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Peugh Brian R.
Yoo Do Hyun
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