Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2004-01-27
2009-06-23
Sough, Hyung S (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S158000, C711S168000, C711S169000
Reexamination Certificate
active
07552301
ABSTRACT:
An information processing apparatus is provided which includes a processor for carrying out a pipeline processing over an instruction, a memory provided in the processor and input/output control means for giving access to the memory with a high priority, a memory access arranging method includes a step of causing a clock to be supplied to the processor to wait when a contention of access of the processor and the input/output control means to the memory is generated, a step of executing the access of the input/output control means to the memory, and a step of canceling the clock wait of the processor after ending the access of the input/output control means to the memory, and executing the access of the processor to the memory.
REFERENCES:
patent: 3603935 (1971-09-01), Moore
patent: 4096571 (1978-06-01), Vander Mey
patent: 4257095 (1981-03-01), Nadir
patent: 4271467 (1981-06-01), Holtey
patent: 4780843 (1988-10-01), Tietjen
patent: 4847757 (1989-07-01), Smith
patent: 5671393 (1997-09-01), Yamaki et al.
patent: 6006303 (1999-12-01), Barnaby et al.
patent: 6065102 (2000-05-01), Peters et al.
patent: 6125421 (2000-09-01), Roy
patent: 6205523 (2001-03-01), Joffe et al.
patent: 6292807 (2001-09-01), Larson
patent: 6480904 (2002-11-01), Kato et al.
patent: 6487643 (2002-11-01), Khare et al.
patent: 6499087 (2002-12-01), Fadavi-Ardekani et al.
patent: 6557085 (2003-04-01), Mattausch
patent: 6629220 (2003-09-01), Dyer
patent: 2170624 (1986-08-01), None
patent: 61-049268 (1986-03-01), None
patent: 01-318139 (1989-12-01), None
patent: 9-198298 (1997-07-01), None
patent: 2000-20452 (2001-01-01), None
European Search Report issued in corresponding European Patent Application No. 04001687.5-2210, dated Apr. 2, 2007.
Japanese Office Action with English Translation issued in Japanese Patent Application No. 2003-017437 dated on Apr. 10, 2008.
Eland Shawn
McDermott Will & Emery LLP
Panasonic Corporation
Sough Hyung S
LandOfFree
Information processing apparatus and memory access arranging... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Information processing apparatus and memory access arranging..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Information processing apparatus and memory access arranging... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4146619