Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-10-25
2003-07-15
Beausoliel, Robert (Department: 2785)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S045000, C712S227000
Reexamination Certificate
active
06594782
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an information processing apparatus, and can be preferably applied to an interface unit with an in-circuit emulator (hereinafter referred to as an ICE) in a built-in type micro-controller.
2. Description of the Related Art
When an operation of the CPU is traced, it is necessary to externally output the trace data indicating the actual execution history.
On the other hand, for example, a RISC microcontroller provides an instruction bus and a data bus separately, and a bus width is designed for a larger number of bits so that the operations of the CPU can be performed at a higher speed.
It is hard to actually extend the width of a bus to output trace data based on the above described technology because of an increasing number of pins per package.
Therefore, when the bit width of an address and data used in a micro-controller is 8 or 16 bits for a low speed operation, all trace data can be easily output externally. However, when the bit width of an address and data used in a micro-controller is 32 or 64 bits for a high speed operation at 100 MHZ or more, it is hard to output all trace data externally.
To solve the above described problem, the following technology is applied to the conventional tracing device.
FIG. 1
is a block diagram of the configuration of the conventional tracing device.
In
FIG. 1
,
201
is a micro-controller,
202
is a CPU,
203
is a bus controller,
204
is a tracing module functioning as an interface circuit with an ICE
205
,
205
is an ICE for receiving trace data which is an execution history of the micro-controller
201
, and
206
indicates trace memory storing trace data.
211
is an instruction address bus used by the CPU
202
in fetching an instruction.
212
is a data address bus used by the CPU
202
in accessing data.
213
is a data bus used by the CPU
202
in accessing data.
214
is an external bus of the micro-controller
201
.
215
is a trace bus for outputting an instruction execution status of the CPU
202
to the ICE
205
.
216
is a status output bus for outputting a signal indicating the status of the data output from the trace bus
215
.
217
is a signal line for outputting a wait signal for stopping the CPU
202
when the output of the trace data from the trace bus
215
is delayed.
Assuming that the bit width of the instruction address bus
211
, the instruction address bus
212
, the data bus
213
, and the trace bus
215
is 32 bits, the tracing module
204
outputs only the instruction address output from the instruction address bus
211
to the ICE
205
through the trace bus
215
, and the trace data of only the instruction address is output for each clock. In this case, data access information output from the data address bus
212
and the data bus
213
is not output to the ICE
205
.
On the other hand, when there is a request to simultaneously trace data access information and an instruction address, the tracing module
204
outputs data access information and an instruction address to the trace bus
215
. When instruction access and data access simultaneously arise, the tracing module
204
sets on the CPU
202
a wait for the end of the output of the trace data to prevent the trace data from being lost because the trace bus
215
does not have a sufficient bus width for both access.
FIG. 2
is a block diagram of another configuration of the conventional tracing device.
In
FIG. 2
,
221
is a micro-controller,
222
is a CPU,
223
is a bus controller,
224
is a debug support unit (hereinafter referred to as a DSU) functioning as an interface circuit with an ICE
225
,
225
is an ICE, and
226
is trace memory storing trace data.
231
is an instruction address bus for use by the CPU
222
fetching an instruction,
232
is a data address bus for use by the CPU
222
accessing data,
233
is a data bus for use by the CPU
222
accessing data,
234
is an external bus of the micro-controller
221
,
235
is a trace bus for outputting an instruction execution status of the CPU
222
to the ICE
225
,
236
is a status output bus for outputting a signal indicating the status of the data output from the trace bus
235
, and the internal status of the micro-controller
221
,
237
is a signal line notifying the DSU
224
that the CPU
222
has executed the instruction and executed a branch instruction.
FIG. 3
is a block diagram of the configuration of the DSU
224
shown in FIG.
2
.
In
FIG. 3
,
241
is a buffer for holding an instruction address output from the instruction address bus
231
,
242
is a buffer for holding a data address output from the data address bus
232
,
243
is a buffer holding the data output from the data bus
233
,
244
is a switch for selecting the data output from among the buffers
241
through
243
to the trace bus
235
,
245
is a buffer for holding the data selected by the switch
244
,
246
is a parallel-serial converter for serially outputting the data held by the buffer
245
to the trace bus
235
,
247
is a control circuit for controlling the switch
244
after determining the data output depending on the statuses of the buffers
241
through
243
and the status of the parallel-serial converter
246
, and
248
is an address decoder for detecting the data write to a specific address.
With the configuration, the number of clocks required to output data is fixed in the DSU
224
depending on the type of the data output from the trace bus
235
, and the output of data is not aborted in the middle of the outputting process.
In addition, since the bus width of the trace bus
235
is not sufficient when data access is traced, only the information about the data write to an assignment address of the buffer
243
specified by the user program is selected by the address decoder
248
, and output to the trace bus
235
.
Furthermore, the DSU
224
receives information from the CPU
222
about the execution of an instruction and a branch instruction performed by the CPU
222
. Then, the DSU
224
outputs a branched-to address from the trace bus
235
, and constantly outputs from the status output bus
236
a status for counting the number of execution instructions by the ICE
225
. Upon receipt of the branched-to address and the number of execution instructions from the DSU
224
, the ICE
225
computes the branched-from instruction address and the branched-to instruction address when a branch occurs, and restores the execution history of the user program.
When only instruction execution is traced in the tracing device shown in
FIG. 1
, no wait is set on the CPU
202
. However, when not only instruction execution but also data access is simultaneously traced, a wait can be set on the CPU
202
. Therefore, the speed of operations of the CPU
202
depends on whether or not a tracing process is performed. For example, if a motor is controlled using the micro-controller
201
or serial communications are established, the CPU
202
can normally perform a process when no tracing operation is performed, but the process speed of the CPU
202
cannot be sufficiently high when a tracing operation is performed.
In addition, in the tracing device shown in
FIG. 2
, when the micro-controller
221
is operated in real time, information overflows the buffers
241
through
243
if branches occur at intervals of the number of clocks required for one branch information outputting operation, or if a user performs several data writing operations within a short time at an address specified by the address decoder
248
for debugging. Therefore, the information overflowing the buffers
241
through
243
cannot be output to the ICE
225
side, whereby incurring the problem that instruction execution cannot be traced.
Furthermore, since trace data is serially output from the trace bus
235
, there arises the problem that the band width of the trace bus
235
is not sufficient for tracing data access, and only the information about the data write can be output to an address of the buffer
243
assigned by the user progr
Beausoliel Robert
Bonzo Bryce P.
LandOfFree
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