Information processing apparatus

Details Information processing apparatus Information processing apparatus

1997-03-24

1999-08-24

Le, Dieu-Minh T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

714765, 714769, 714809, G06F 1100

Patent

active

059420014

ABSTRACT:
Channel data obtained from a reproduced signal is input to a demodulation ROM as an address and demodulated. In the demodulated channel data, the data whose data pattern is not consistent with a 2-7 modulation method is recognized as an error data. When a resync code, given in the channel data at every 15 bytes is not detected within a predetermined time period, a resync code undetected signal is generated. The demodulated data is arranged in a matrix, and the position of the error data in the matrix and the resync code undetected generation position are specified. An error correction circuit carries out the error correction (erasure correction) by using these positions and an error correction code relating to one direction of a row or a column of the matrix.

REFERENCES:
patent: 3812531 (1974-05-01), Hall
patent: 4633470 (1986-12-01), Welch et al.
patent: 4760576 (1988-07-01), Sako
patent: 5216677 (1993-06-01), Takagi et al.
patent: 5373513 (1994-12-01), Howe et al.
patent: 5451943 (1995-09-01), Satomura
patent: 5631457 (1997-05-01), Fukuda et al.

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