Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
1999-01-08
2001-07-24
Pan, Daniel H. (Department: 2783)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C712S038000, C712S211000, C711S005000, C711S153000, C711S003000, C710S120000
Reexamination Certificate
active
06266762
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an information processing apparatus, in particular, to an information processing apparatus in which data access is performed using a register bank method (see Japanese Laid-Open Patent Application No. 4-14147).
2. Description of the Related Art
An information processing apparatus in which data access is performed using the register bank method is, as shown in
FIG. 1
, provided with a CPU (Central Processing Unit) body
1
and a register-bank memory
2
having a single port. The CPU body
1
and register-bank memory
2
are connected with each other via a special internal address bus, internal data bus
4
and control-signal line
5
, other than the data bus and address bus used for connecting with peripheral apparatuses.
The CPU body
1
includes:
a general-use register set (register array)
6
which is made of a plurality of registers;
a special register (CBNR)
7
which specifies bank numbers of the register-bank memory
2
;
a bank address buffer
8
which integrates signals, which indicate currently used bank numbers of banks in a memory unit
13
of the register-bank memory
2
and are obtained from the special register
7
, with register selection control signals RGS
0
through RGSn which indicates register numbers of registers in the banks (ordinarily, a plurality of registers being included in a bank), and thus supplies signals RA
0
through RAm to the register-bank memory
2
;
an address circuit
9
to which the current bank numbers and RGS
0
through RGSn are input;
a decoding circuit
10
to which these signals are input from the address circuit
9
;
a command control unit
11
which supplies signals including RBCK (control clock signal), RBCE (memory enable signal), RBWEB (read/write control signal) to the register-bank memory
2
; and
an input/output circuit
12
which sends to and receives from the register-bank memory
2
RB
0
through RBn (register data).
The address circuit
9
has, as shown in
FIG. 2
, circuits including inverters for the RGS
0
through RGSn, receives the RGS
0
through RGSn, and supplies forward and inverse signals thereof (IA
0
through IAn and IA
0
B through IAnB in FIG.
2
). Further, the decoding circuit
10
is, as shown in
FIG. 3
, made of four-input NAND circuits and inverters, receives output (IA
0
through IA
3
and IA
0
B through IA
3
B in FIG.
3
), and supplies decoded signals (RG
0
through RG
15
in FIG.
3
).
The register-bank memory
2
includes:
a memory unit
13
;
an address circuit
14
which receives the above-mentioned RA
0
through RAm;
a decoding circuit
15
which receives the forward and inverse outputs from the address circuit
14
;
a control circuit
16
which receives the above-mentioned signals including RBCK, RBCE and RBWEB and controls the address circuit
14
; and
an input/output circuit
17
which sends to and receives from the register-bank memory
2
the above-mentioned RB
0
through RBn.
The above-mentioned address circuit
14
includes, as shown in
FIG. 4
, circuits made of a NAND circuit and an inverter, receives from the above-mentioned bank address buffer
8
the RA
0
through RAm and supplies the forward and inverse signals thereof (IA
0
through IAm and IA
0
B through IAmB in the figure). Input signals RA
0
through RAm relevant to the above-mentioned RGS
0
through RGSn in the CPU body
1
, and RAn+
1
through RAm correspond to the current bank numbers starting from CBNR
7
in the CPU body
1
. Further, a signal ICE shown in
FIG. 4
is supplied by the control circuit
16
and controls driving of the address circuit
14
.
The decoding circuit
15
includes, as shown in
FIG. 5
, five-input NAND circuits receiving signals from the address circuit
14
and NOR circuits, and receives outputs (IA
0
B through IA
4
B and IA
0
through IA
4
in the figure) from the address circuit
14
, and outputs decoded signals (WL
0
through WL
31
in the figure).
The memory unit
13
includes, as shown in
FIG. 6
, a memory-cell array unit
13
a
and a precharging unit
13
b
, and is provided with a memory space corresponding to a memory space of the general-use register set
6
. Further, the memory unit
13
sends to and receives from the decoding circuit the decoded signals (WL
0
through WLn-
1
in the figure), and sends to and receives from the input/output circuit
17
the signals (BL
0
through BLm-
1
, BLB
0
through BLBm-
1
in the figure). A signal ICKB shown in the figure is supplied by the control circuit
16
and controls the precharging.
The input/output circuit
17
includes, as shown in
FIG. 7
, a writing circuit
17
a
. The input/output circuit
17
sends to and receives from the memory unit
13
the signals (BL
0
through BLm-
1
, BLB
0
through BLBm-
1
), and also sends to and receives from the input/output circuit
12
in the CPU body
1
data (RB
0
through RBn). A signal IWE shown in the figure is supplied by the control circuit
16
and controls reading/writing.
The control circuit
16
includes, as shown in
FIG. 8
, NAND circuits and inverters and receives from the command control unit
11
in the CPU body
1
the signals RBCK, RBCE and RBWEB, and outputs the control signals ICE, ICKB and IWE.
FIG. 9
shows the timing of reading/writing and precharging of the precharging unit
13
b
in the memory unit
13
. When the signal RBCK from the CPU body
1
is at a low level, the signal ICKB is at a high level and all of the memory cells (MC) are thus precharged. When the ICKB is in the high level, none of the signals WL
0
through WLn-
1
are selected (see FIG.
5
). Further, when the signal RBCK is at the high level, according to a current address, one of the signals WL
0
through WLn-
1
is selected. When, in this state, the signal RBWEB is at the low level, the signal IWE is at the high level and a writing operation is performed on the memory cells. When, in the same state, the signal RBWEB is at the high level, the IWE signal is at the low level and a reading operation is performed on the memory cells. The signal RBCE is maintained to be at the high level during a register accessing operation.
The above-described information processing apparatus in the related art using the register bank method operates as described below.
When the CPU body
1
executes a command and reads data from the registers, data in the general-use register set
6
is read out. At this time, the register-bank memory
2
has the signals RA
0
through RAm supplied thereto from the bank address buffer
8
and thus enters a read state. However, the CPU body
1
gives a higher priority to and therefore receives data read from the general-use register set
6
, not data read from the register-bank memory
2
.
When the CPU body
1
executes a command and writes data to registers, data is written in the general-use register set
6
, and simultaneously the same data is written in a memory region, corresponding to a bank number currently being used, of the general-use register set
6
, in the register-bank memory
2
. For example, when the command to be executed is an adding command (a result of (R
2
+R
15
) is stored as R
15
, that is, ‘add: g. 1 r2, r15’ in a programming language), after a calculation of (R
2
+R
15
) is performed, the result is written in a register R
15
of the general-use register set
6
and simultaneously the same result is written in a region for the register R
15
in the register-bank memory
2
.
Thus, the register-bank memory
2
has data the same as that which the general-use register set
6
has, in relevant regions thereof.
A case where the information processing apparatus did not use the above-described register bank method will now be considered. In such a case, data currently being stored in the general-use register set
6
and being currently used may be switched to other new data stored in a new bank of externally provided memory. Such an operation may be referred to as register bank switching. When the register bank switching is performed, the data, which is the same as that currently being stor
Aota Hideyuki
Yoshioka Keiichi
Cooper & Dunham LLP
Pan Daniel H.
Ricoh & Company, Ltd.
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